High-Temperature Recessed Channel SiC CMOS Inverters and Ring Oscillators

Abstract

Digital electronics in SiC find use in hightemperature applications. The objective of this study was to fabricate SiC CMOS without using ion implantation. In this letter, we present a recessed channel CMOS process. Selective doping is achieved by etching epitaxial layers into mesas. A deposited SiO 2 -film, post-annealed at low temperature and re-oxidized in pyrogenic steam, is used as the gate oxide to produce a conformal gate oxide over the non-planar topography. PMOS, NMOS, inverters, and ring oscillators are characterized at 200 • C. The PMOS requires reduced threshold voltage in order to enable longterm reliability. This result demonstrates that it is possible to fabricate SiC CMOS without ion implantation and by low-temperature processing.

Ultrafast Pulsed <i>I-V</i> and Charge Pumping Interface Characterization of Low-Voltage <i>n</i>-Channel SiC MOSFETs

“…In our previous work, we reported lateral lowvoltage recessed channel transistors intended for hightemperature integrated circuits [6,7]. In this work, we present the results of the pulsed charac terization of the interface and nearinterface defects found in these transistors.…”

“…Nitridation by nitrous oxide (N 2 O) or by nitric oxide (NO) is a common method to achieve highperformance NMOS transistors (mobilities around 25-35 cm 2 /Vs) [1,17]. The low temperature and short times were motivated by reducing excessive oxidation on the exposed afaces present in the recessed channel design [6,7]. Insitu doped polysilicon (ntype) was used as gate electrode.…”

“…Insitu doped polysilicon (ntype) was used as gate electrode. All three processes gave a capacitance equivalent thickness (CET) of ∼34 nm, estimated by split CV method on large channel area transistors (100 µm × 100 µm), and using the maximum inversion capacitance as a measure of gate oxide capacitance (C ox ) [6,7]. Details on the other process steps can be found in [6,7].…”

“…All three processes gave a capacitance equivalent thickness (CET) of ∼34 nm, estimated by split CV method on large channel area transistors (100 µm × 100 µm), and using the maximum inversion capacitance as a measure of gate oxide capacitance (C ox ) [6,7]. Details on the other process steps can be found in [6,7]. N channel transistors of 100 µm width and 2 µm channel length were electrically characterized at 200 • C to investigate their use for hightemperature applications using a Keithley 4200SCS con nected to a semiautomatic Cascade 12000 probestation.…”

Demonstration of Monolithic Polycrystalline Diamond-GaN Complementary FET Technology for High-Temperature Applications

“…Wide-band gap (WBG) and ultrawide-band gap (UWBG) semiconductors can fulfill the need for high-temperature operation of integrated circuits by providing sufficient stability without complex cooling needs. Extended operating temperatures have been demonstrated in silicon carbide (SiC) complementary metal-oxide semiconductor (CMOS) technology. − However, the low mobilities in both n- and p-type lateral SiC field-effect transistors (FETs) limit the potential for high-frequency applications. , While gallium nitride (GaN) is a well-known channel material in high-electron mobility transistors (HEMT), hydrogen-terminated diamond hole FETs can offer a hole mobility above 300 cm 2 V –1 s –1 . Thus, complementary channels offered by these two wide bandgap materials make an attractive combination and form the basis of our work here.…”