High speed true random number generator based on open loop structures in FPGAs

Danger, Jean‐Luc; Guilley, Sylvain; Hoogvorst, Philippe

doi:10.1016/j.mejo.2009.02.004

Cited by 86 publications

(28 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…This is because synchronous flip-flops are hardwired in logic cells as optimized blocks and their metastable behavior is consequently minimized. On the other hand, latches can usually only be implemented in Look up tables (LUTs) and are therefore subject to metastable behavior to a greater extent [7].…”

Section: Methods Of Randomness Extractionmentioning

confidence: 99%

See 1 more Smart Citation

A Closer Look at Security in Random Number Generators Design

Fischer

2012

Constructive Side-Channel Analysis and Secure Design

View full text Add to dashboard Cite

Abstract. The issue of random number generation is crucial for the implementation of cryptographic systems. Random numbers are often used in key generation processes, authentication protocols, zeroknowledge protocols, padding, in many digital signature and encryption schemes, and even in some side channel attack countermeasures. For these applications, security depends to a great extent on the quality of the source of randomness and on the way this source is exploited. The quality of the generated numbers is checked by statistical tests. In addition to the good statistical properties of the obtained numbers, the output of the generator used in cryptography must be unpredictable. Besides quality and unpredictability requirements, the generator must be robust against aging effects and intentional or unintentional environmental variations, such as temperature, power supply, electromagnetic emanations, etc. In this paper, we discuss practical aspects of a true random number generator design. Special attention is given to the analysis of security requirements and on the way how this requirements can be met in practice.

show abstract

Section: Methods Of Randomness Extractionmentioning

confidence: 99%

“…These variations can be seen as a clock period instability (the jitter) in clock generators containing delay elements assembled in a closed loop (ring oscillators). The variation in propagation time is also used in generators with delay elements in an open chain assembly [7].…”

Section: Source Of Randomnessmentioning

confidence: 99%

A Closer Look at Security in Random Number Generators Design

Fischer

2012

Constructive Side-Channel Analysis and Secure Design

View full text Add to dashboard Cite

show abstract

“…Furthermore, Danger has proposed his work using the metastability based TRNG structure [8]. As an open-loop circuit, this scheme used the delay chain to capture the metastability behavior from the D-latch adopted on the delay chain.…”

Section: A Related Workmentioning

confidence: 99%

A complementary architecture for high-speed true random number generator

Xian

Cheung

2014

2014 International Conference on Field-Programmable Technology (FPT)

View full text Add to dashboard Cite

In this paper, we introduce a novel FPGA-based design for true random number generator (TRNG). It is able to harvest the timing difference caused by the nonuniformity of the Integrated Circuits (ICs) and use it to generate the randomness. Compared with the previous related work, this design uses a complementary scheme that leads to a doubled data rated output. The proposed complementary design has improved entropy and achieved higher throughput. The prototype design has been implemented and verified on a Xilinx Virtex-6 ML605 evaluation board. As a result, the generated random number stream is able to pass the statistical NIST and DIEHARD test suites showing a reliable performance. Meanwhile, it can approach the maximum data rate as 50 Mbps stably.

show abstract

“…Unfortunately jitter based generators are very susceptible to external conditions and internal conditions like temperature, accumulation of charges or the manufacturing process. Multiple papers have already shown [3][4][5][6] that most implementations are required to be precisely calibrated by hand in order to achieve the best performance. This calibration is made statically and limits the usability of such implementations.…”

Section: Introductionmentioning

confidence: 99%

FPGA based TRNG using automatic calibration

Haller

Suciu

Cret

2009

2009 IEEE 5th International Conference on Intelligent Computer Communication and Processing

View full text Add to dashboard Cite

This paper presents a new method to improve the quality of True Random Number Generators implemented on Field Programmable Gate Arrays.Traditionally implementations require an exact manual calibration to achieve the best performance. In this paper we are suggesting a method which uses modern clocking features to perform automatic calibration. This feature also enable the efficient use of some jitter sources previously unavailable to designers. The present design also uses one of these sources, the jitter available on the clock lines. The implementation has the advantage of a relatively high throughput in a small size. The quality of the generated stream is also high, passing multiple test suites. The implementation is also provided as a calibrating framework which can be easily reused for other designs.

show abstract

High speed true random number generator based on open loop structures in FPGAs

Cited by 86 publications

References 13 publications

A Closer Look at Security in Random Number Generators Design

A Closer Look at Security in Random Number Generators Design

A complementary architecture for high-speed true random number generator

FPGA based TRNG using automatic calibration

Contact Info

Product

Resources

About