High-speed parallel CRC circuits

Kennedy, Christopher; Reyhani-Masoleh, Arash

doi:10.1109/acssc.2008.5074742

Cited by 18 publications

(26 citation statements)

References 24 publications

(76 reference statements)

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“…We note that this presentation is similar to the generalized parallel LFSR2 derivation contained in [9].…”

Section: Parallel Lfsr1 Crc Formulationmentioning

confidence: 75%

“…Observing the formulation presented in the previous section, we note that there does not exist any feedback in (9). Therefore, one can freely retime the modular reduction of the intermediate by the generator polynomial to a desired number of XOR gate delays.…”

Section: Retimed Two-step Crc Computation Architecturementioning

confidence: 98%

“…2. The first block is denoted by x and realizes (8), while the second block is denoted by y and realizes (9).…”

Section: Two-step Crc Computation Architecturementioning

confidence: 99%

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Retimed two-step CRC computation on FPGA

2010

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Previously, a two-step approach to perform the cyclic redundancy check (CRC) computation in hardware was presented. In that approach, an architecture is constructed from a suitable multiple polynomial for a fixed generator polynomial and input size. In this paper, we revisit the two-step approach and suggest a modification to its architecture. First, we propose retiming the second step to the delay of the first step in order to obtain a parallel CRC computation architecture with minimal critical path delay. Next, we propose a software algorithm to find multiple polynomials and identify ones for some useful cases. Finally, implementations are carried out on a Xilinx Virtex-5 field-programmable gate array (FPGA) device, comparing the proposed architecture with the original. As expected, the proposed architecture demonstrates improvements in timing at the cost of additional area.

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“…We note that this presentation is similar to the generalized parallel LFSR2 derivation contained in [9].…”

Section: Parallel Lfsr1 Crc Formulationmentioning

confidence: 75%

Section: Retimed Two-step Crc Computation Architecturementioning

confidence: 98%

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Retimed two-step CRC computation on FPGA

2010

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“…Here, we provide a generalized recursive binary polynomial-based formulation for the non-retimed parallel LFSR2 CRC architecture, similar to the derivation contained in [20]. In Section III, this formulation will be further generalized.…”

Section: Name Polynomialmentioning

confidence: 99%

Generalized parallel CRC computation on FPGA

Kennedy¹,

Kermani

2015

2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE)

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The cyclic redundancy check (CRC) is a popular error detection code (EDC) used in many digital transmission and storage protocols. Most existing digit-serial hardware CRC computation architectures are based on one of the two wellknown bit-serial CRC linear feedback shift register (LFSR) architectures. In this paper, we present and investigate a generalized CRC formulation that incorporates negative degree terms. Through software simulations, we identify useful formulations that result in reduced time and/or area complexity CRC circuits compared to the existing non-retimed approaches. Implementation results on an Altera field-programmable gate array (FPGA) device are reported. We conclude that the proposed approach is most effective when the digit size is greater than the generator polynomial degree.

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“…With all other tested benchmarks, CRC-32's accuracy never exceeds 70%. Considering the complexity of a parallel CRC-32 implementation [5,11] and its unremarkable detection performance, we believe it is not the ideal choice for our goals. Figure 5 plots the findings of this experiments.…”

Section: Detection Accuracymentioning

confidence: 99%

ArChiVED: Architectural checking via event digests for high performance validation

Hsu

Chatterjee

Morad

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-Simulation-based techniques play a key role in validating the functional correctness of microprocessor designs. A common approach for validating microprocessors (called instruction-by-instruction, or IBI checking) consists of running a RTL and an architectural simulation in lock-step, while comparing processor architectural state at each instruction retirement. This solution, however, cannot be deployed on long regression tests, because of the limited performance of RTL simulators. Acceleration platforms have the performance power to overcome this issue, but are not amenable to the deployment of an IBI checking methodology. Indeed, validation on these platforms requires logging activity on-platform and then checking it against a golden model off-platform. Unfortunately, an IBI checking approach following this paradigm entails a large slowdown for the acceleration platform, because of the sizable amount of data that must be transferred off-platform for comparison against the golden model. In this work we propose a sequence-by-sequence (SBS) checking approach that is efficient and practical for acceleration platforms. Our solution validates the test execution over sequences of instructions (instead of individual ones), thus greatly reducing the amount of data transferred for off-platform checking. We found that SBS checking delivers the same bug-detection accuracy as traditional IBI checking, while reducing the amount of traced data by more than 90%.

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High-speed parallel CRC circuits

Cited by 18 publications

References 24 publications

Retimed two-step CRC computation on FPGA

Retimed two-step CRC computation on FPGA

Generalized parallel CRC computation on FPGA

ArChiVED: Architectural checking via event digests for high performance validation

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