High-Speed Modular Multiplier for Lattice-Based Cryptosystems

Tan, Weihang; Case, Benjamin M.; Wang, Antian; Gao, Shuhong; Lao, Yingjie

doi:10.1109/tcsii.2021.3064232

Cited by 17 publications

(2 citation statements)

References 15 publications

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“…A CRT-friendly modulus leads to an optimized hardware architecture with respect to the overall timing and area performance for the pre-processing and post-processing steps. Our exhaustive approach generates q i that are similar to the Solinas prime, and contain a few signed power-of-two terms [29], [30].…”

Section: A Special Ntt-compatible and Crt-friendly Primes Selectionmentioning

confidence: 99%

PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption

Tan¹,

Chiu²,

Wang³

et al. 2023

Preprint

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High-speed long polynomial multiplication is important for applications in homomorphic encryption (HE) and lattice-based cryptosystems. This paper addresses low-latency hardware architectures for long polynomial modular multiplication using the number-theoretic transform (NTT) and inverse NTT (iNTT). Chinese remainder theorem (CRT) is used to decompose the modulus into multiple smaller moduli. Our proposed architecture, namely PaReNTT, makes four novel contributions. First, parallel NTT and iNTT architectures are proposed to reduce the number of clock cycles to process the polynomials. This can enable real-time processing for HE applications, as the number of clock cycles to process the polynomial is inversely proportional to the level of parallelism. Second, the proposed architecture eliminates the need for permuting the NTT outputs before their product is input to the iNTT. This reduces latency by n/4 clock cycles, where n is the length of the polynomial, and reduces buffer requirement by one delay-switch-delay circuit of size n. Third, an approach to select special moduli is presented where the moduli can be expressed in terms of a few signed powerof-two terms. Fourth, novel architectures for pre-processing for computing residual polynomials using the CRT and postprocessing for combining the residual polynomials are proposed. These architectures significantly reduce the area consumption of the pre-processing and post-processing steps. The proposed long modular polynomial multiplications are ideal for applications that require low latency and high sample rate as these feedforward architectures can be pipelined at arbitrary levels. The experimental results show that the proposed architecture reduces the area-block processing product (ABP) by a factor of 43.2 times with respect to LUT and 11.5 times with respect to DSP, when compared without the use of CRT, for a polynomial degree of 4096 and word-length of 192 bits, for a two-parallel architecture.

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Section: A Special Ntt-compatible and Crt-friendly Primes Selectionmentioning

confidence: 99%

PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption

Tan¹,

Chiu²,

Wang³

et al. 2023

Preprint

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“…The speed of the processor is majorly determined by the processing speed of multipliers [7]. Hence, parallel and reconfigurable Field Programmable Gate Array (FPGA) based hardware architectures are needed to be designed.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of FPGA Based Complex Floating Point Multiplier using CIFM

et al. 2023

IJFMR

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: Floating point multiplication is one of the crucial operations in many application domains such as image processing, signal processing etc. But every application requires different working features. Some need high precision, some need low power consumption, low latency etc. The multiplication process requires more hardware resources and processing time when compared with addition and subtraction. This paper presents, Design and Implementation of FPGA based Complex Floating Point Multiplier using Combined Integer and Floating point Multiplier (CIFM). The Processing speed of the multipliers decides the execution time of the system as it consumes most of the time. The design is implemented in VHDL and design is synthesized on FPGA to know the performance. The architectures for the three multiplier solutions of complex multiplier for 32 x 32 bit complex numbers multiplication are coded in VHDL and implemented through Xilinx ISE 13.4 navigator and Modelsim 5.6 and their performance is compared. The complex floating point multiplication with single precision using CIFM multiplier has comparatively less amount of delay and power consumption with respect to Vedic and Array multiplier.

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Efficient Hardware Implementation Architectures for Long Integer Modular Multiplication over General Solinas Prime

Huai

Zhou

Zhang

2022

J Sign Process Syst

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High-Speed Modular Multiplier for Lattice-Based Cryptosystems

Cited by 17 publications

References 15 publications

PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption

PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption

Design and Implementation of FPGA Based Complex Floating Point Multiplier using CIFM

Efficient Hardware Implementation Architectures for Long Integer Modular Multiplication over General Solinas Prime

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