High-Speed Memristor-Based Ripple Carry Adders in 1T1R Array Structure

Fu, Xingzhi; Li, Qingjiang; Wang, Weihe; Xu, Hui; Wang, Yinan; Wang, Wei; Yu, Hao; Li, Zhiwei

doi:10.1109/tcsii.2022.3174219

Cited by 5 publications

(2 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The hierarchical design of a signal processing block consists of sub-systems such as multipliers and adders that form the fundamental building block for any signal processing unit. In this chapter, a literature review on the design and analysis of various multipliers and adders is presented [8][9][10]. The adder function is used in the majority of applications.…”

Section: Literature Surveymentioning

confidence: 99%

Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications

2024

Teh. vjesn.

View full text Add to dashboard Cite

This research focuses on critical hardware components of an Internet of Things (IoT) system for reconfigurable processing systems. Single-Instruction Multiple-Data (SIMD) processors have recently been utilized to preprocess data at energy-constrained sensor nodes or IoT gateways, saving significant energy and bandwidth for transmission. Using traditional CPU-based systems to implement machine learning algorithms is inefficient in terms of energy consumption. In the proposed method Single-Instruction Multiple-Data (SIMD) processors are assembled by scaling the largest possible operand value subunits into direct access to the internal memory, where the carry output of each unit is conditionally fed into the next unit based on the implementation of the SIMD Processor design for Internet of Things applications. Each method has evaluated sub-operations that contribute considerably to the overall potential of the design. If the single register file can complete the intended action, a zero (one)-signal is applied to each unit's carry input. Multiplexers combine two or more adders, sending the carry signal from one unit into another if additional units are necessary to compute the sum. The outcome results compare high-speed end device techniques in terms of area and power consumption. The proposed SIMD processor-based IoT healthcare monitoring system with a MIMD processor's performance analysis of comparison clearly demonstrates that the system produces decent outcomes. The suggested system has an area overhead of 85 m 2 , a power usage of 4.10 W, and a time delay of 20 ns.

show abstract

Section: Literature Surveymentioning

confidence: 99%

Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications

2024

Teh. vjesn.

View full text Add to dashboard Cite

show abstract

“…The main idea of our proposed method is analysing margin of stateful logic design according to the extreme cases, and chooses suitable devices. It can be applied not only for 3-OR and 3-NAND gate, but for all design based on the principle of stateful logic, like CCAU in [14]. It is important to note that, our analysis excludes the case that the output memristor cannot perform set and reset operations due to a failure of the memristor.…”

Section: -Bit Full Addermentioning

confidence: 99%

Margin‐based reliability reinforcement method for stateful logic

Wang

et al. 2022

Electronics Letters

View full text Add to dashboard Cite

The memristive stateful logic can realize the memory and computation, thus effectively avoid the huge time and energy overhead caused by data moving between memory and computation units. However, the memristive stateful logic still faces the reliability challenges caused by the variability of memristor, which prevents it from practical applications. A reliability reinforcement method with low overhead in delay, area and peripheral circuits is thus needed to be studied urgently. This paper proposes a novel method of reliability reinforcement based on logic gates' margin. By optimizing circuit structure and driving voltage configuration, the margin of logic gates is improved to tolerant memristors' variability to the maximum extent, and thus reinforces logic gates' reliability. Simulations demonstrate that the proposed method can improve the allowed threshold variability range by 42% and 92% for 2-input NAND gate and 2-input OR gate, respectively. Benchmark with other methods shows that the proposed margin-based reinforcement method achieves almost the same reliability reinforcement effect, but the overhead in area and peripheral circuit is greatly reduced.

show abstract

Crossbar array based on tri-valued memristors: its design and application

Wang,

Bao,

et al. 2024

Nonlinear Dyn

View full text Add to dashboard Cite

High-Speed Memristor-Based Ripple Carry Adders in 1T1R Array Structure

Cited by 5 publications

References 21 publications

Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications

Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications

Margin‐based reliability reinforcement method for stateful logic

Crossbar array based on tri-valued memristors: its design and application

Contact Info

Product

Resources

About