High speed low voltage low power embedded analog-to-digital converters for wideband transceivers

Abstract

The analog-to-digital converter (ADC) is one of the key building blocks in digital communication systems. In modern receiver designs, ADCs are usually fabricated on the same die with the digital baseband signal processing block for the dual-chip solution. This implementation takes into considerations of cost, flexibility and packaging. The combination of analog circuits and digital circuits in one die poses numerous challenges in ADC design due to the coupling of digital noise to analog circuits. Currently, the fast growing demands for high data rate applications in multimedia services are calling for faster baseband circuits. With the advancement of the CMOS process, both the transistor channel length and supply voltage are shrinking, making faster digital circuits possible. However, unlike their digital counterparts, the analog circuits do not always benefit from the technology evolution in terms of accuracy, speed and power consumption. Although process advancement improves the transistor's unity gain frequency it, device scaling decreases the transistor intrinsic gain, making the design of high accuracy analog circuits difficult in the deep sub-micron process. Obviously the decrease of supply voltage lowers the signal-to-noise ratio since the signal amplitude has to be decreased accordingly while the noise level remains the same. The dropping in signal-to-noise ratio is another major challenge in ADC design as the technology heading toward the nanometer.