High speed low power multiple bit subtracter circuit design using high performance domino logic

Sivasankari, S.; Ajayan, J.; Sivaranjani, D.

doi:10.1109/icices.2014.7034066

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High speed low power multiple bit subtracter circuit design using high performance domino logic

Cited by 2 publications

References 12 publications

Voltage deviate-domino circuits for low power high-speed applications using prescient innovation model

Voltage deviate-domino circuits for low power high-speed applications using prescient innovation model

Investigation on Power Supply Scaling Effects on the Performance of PET/NET TSPC-DATA-Flip Flops at Wide Range of Operating Temperatures

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