High speed, low power 100 MS/s front end track-and-hold amplifier for ten-bit pipelined ADC

Meganathan, D.; Perinbam, Raja Paul; Deepalakshmi, R.

doi:10.1504/ijhpsa.2009.030094

Cited by 3 publications

(2 citation statements)

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“…The designed 10-bit pipelined ADC comprises several sub-blocks including parallel sampling MDAC, Op-amp sharing MDAC, Dynamic Comparator, 4-bit and 2-bit Flash ADC and digital error correction (DEC) logic. In the parallel sampling technique, the input analog signal and the word size of the restored signal is greater than sub-ADC (Meganathan et al , 2009). Both of the sub-ADCs are designed with the same resolution, the sampled signal proved to have an improved SNDR ratio than the signal in the secondary path due to the increased input signal swing (Meganathan et al , 2009).…”

Section: Resultsmentioning

confidence: 99%

“…In the parallel sampling technique, the input analog signal and the word size of the restored signal is greater than sub-ADC (Meganathan et al , 2009). Both of the sub-ADCs are designed with the same resolution, the sampled signal proved to have an improved SNDR ratio than the signal in the secondary path due to the increased input signal swing (Meganathan et al , 2009). When processing the large input signal, this signal need not go through the sub-ADC.…”

Section: Resultsmentioning

confidence: 99%

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A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique

Sam

Paul

2021

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Purpose In parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC. Design/methodology/approach Various low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique. Findings This paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent. Originality/value Simulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%