High-speed low-complexity Reed-Solomon decoder using pipelined Berlekamp-Massey algorithm

Park, Jeong-In; Lee, Kihoon; Choi, Chang Soo; Lee, Hanho

doi:10.1109/socdc.2009.5423927

Cited by 15 publications

(12 citation statements)

References 7 publications

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“…In order not to have to do this costly calculation, many authors have come up with modified versions of the algorithm, e.g. [20][21][22]. However, these are all time-memory tradeoffs of the original inversionless BM algorithm by Burton [5], which we prefer due to its lower storage requirements.…”

Section: Bch Decodingmentioning

confidence: 99%

“…Most BCH decoders are designed with a focus on throughput and use systolic array designs, e.g. [19,20,22]. Aiming for a size-optimized implementation, we propose a serialized, minimalistic coprocessor design with a 10-bit application-specific instruction set and limited conditional execution support.…”

Section: Syndrome Generation and Error Decoding For C Rep And C Bchmentioning

confidence: 99%

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PUFKY: A Fully Functional PUF-Based Cryptographic Key Generator

Maes

Herrewege

Verbauwhede

2012

Cryptographic Hardware and Embedded Systems – CHES 2012

209

216

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Abstract. We present PUFKY: a practical and modular design for a cryptographic key generator based on a Physically Unclonable Function (PUF). A fully functional reference implementation is developed and successfully evaluated on a substantial set of FPGA devices. It uses a highly optimized ring oscillator PUF (ROPUF) design, producing responses with up to 99% entropy. A very high key reliability is guaranteed by a syndrome construction secure sketch using an efficient and extremely low-overhead BCH decoder. This first complete implementation of a PUF-based key generator, including a PUF, a BCH decoder and a cryptographic entropy accumulator, utilizes merely 17% (1162 slices) of the available resources on a low-end FPGA, of which 82% are occupied by the ROPUF and only 18% by the key generation logic. PUFKY is able to produce a cryptographically secure 128-bit key with a failure rate < 10 −9 in 5.62 ms. The design's modularity allows for rapid and scalable adaptations for other PUF implementations or for alternative key requirements. The presented PUFKY core is immediately deployable in an embedded system, e.g. by connecting it to an embedded microcontroller through a convenient bus interface.

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Section: Bch Decodingmentioning

confidence: 99%

Section: Syndrome Generation and Error Decoding For C Rep And C Bchmentioning

confidence: 99%

PUFKY: A Fully Functional PUF-Based Cryptographic Key Generator

Maes

Herrewege

Verbauwhede

2012

Cryptographic Hardware and Embedded Systems – CHES 2012

209

216

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“…This is due to the target application of our design: PUF key extraction. The primary goal of our design is compactness, for existing designs it is high throughput [11][12][13][15][16][17]. Further complicating this is that the area of other implementations are either given for an ASIC implementation [11,15,16] or simply not stated [12,13,17].…”

Section: Methodsmentioning

confidence: 99%

“…The primary goal of our design is compactness, for existing designs it is high throughput [11][12][13][15][16][17]. Further complicating this is that the area of other implementations are either given for an ASIC implementation [11,15,16] or simply not stated [12,13,17]. Furthermore, the codes used for our target application are generally defined over F 2 u where 8 ≤ u ≤ 10, with high error correcting capabilities of 3-10% [3][4][5], and our firmware is optimized with this in mind.…”

Section: Methodsmentioning

confidence: 99%

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Tiny application-specific programmable processor for BCH decoding

Herrewege

Verbauwhede

2012

2012 International Symposium on System on Chip (SoC)

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Abstract-We present a novel design for a tiny application-specific programmable processor for BCH decoding. The design is optimized for use in a PUF key extractor, where low-area overhead is extremely important. Due to it's flexible nature, it can support a wide range of BCH codes. The complete design for a BCH(413, 296, 13) decoder requires only 1% (less than 70 slices) of the available resources of a small FPGA.

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