High-speed KATAN ciphers on-a-chip

Abstract

Security in embedded systems has become a main requirement in modern electronic devices. The demand for low-cost and highly secure cryptographic algorithms is increasingly growing in fields such as mobile telecommunications, handheld devices, etc. In this paper, we analyze and evaluate the development of cheap and relatively fast hardware implementations of the KATAN family of block ciphers. KATAN is a family of six hardware oriented block ciphers. All KATAN ciphers share an 80-bit key and have 32, 48, or 64-bit blocks. We use VHDL under Altera Quartus in conjunction with ModelSim to implement and analyze our hardware designs. The developed designs are mapped onto high-performance Field Programmable Gate Arrays. We compare our findings with similar hardware implementations and C software versions of the algorithms. The performance analysis of the C implementations is done using Intel Vtune Amplifier running on Dell precision T7500 with its dual quadcore Xeon processor and 24 GB of RAM. The obtained results show better performance when compared with existing hardware and software implementations.

Analysis of Pipelined KATAN Ciphers under Handle-C for FPGAs

“…The parallel-pipelined implementation speed ups are bigger than sequential implementation speedups, but the 32-bit KATAN is an anomaly to the pattern with the largest speed up of 263.67 as seen in Fig. 3 As can be seen in Table V and Table VI, the behavioral design and pipeline designs from [21] respectively are significantly faster in comparison to our design. This was expected as our designs have smaller clock periods but larger number of clock cycles whereas both the behavioral and pipeline implementations in [21] have smaller number of clock cycles but larger clock periods.…”

“…This was expected as our designs have smaller clock periods but larger number of clock cycles whereas both the behavioral and pipeline implementations in [21] have smaller number of clock cycles but larger clock periods. In other words, comparing our designs with [21] reveals the flaw in highlevel design tools like Handel-C. Even though Handel-C allows for faster implementation and saves time, but tradeoffs in terms of control over the clock cycle and clock period must be made.…”

“…2. Next, the parallel-pipelined hybrid implementations are compared to the original [7] as well as the behavioral and pipelined implementations of Qatan et al [21].…”

Hardware design and modeling of lightweight block ciphers for secure communications

“…Qatan and Damaj [43] studied the FPGA implementation of KATAN and KTANTAN ciphers focusing on the speed and area metrics, but it did not include any power or energy analysis.…”

Optimization and modeling of FPGA implementation of the Katan Cipher

“…[10] presented ASIC design results with emphasis on area and speed. [17] discussed the FPGA implementation of the Katan cipher with emphasis on area and speed. Clearly, no comprehensive study was conducted on the power and energy dissipation of Katan FPGA design.…”