High speed IDDQ test and its testability for process variation

Abstract

A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production.

Investigation into voltage and process variation-aware manufacturing test

“…Current-based testing in the presence of process variation has been addressed in [152,153,53]. The impact of process variation on IDDQ testing for bridges was measured in [152] for a small adder circuit.…”

“…The impact of process variation on IDDQ testing for bridges was measured in [152] for a small adder circuit. The fault coverage was significantly reduced for 10% variation on VT and likewise for 3% variation on the W/L ratio (W and L are the width and length dimensions of a transistor gate).…”

“…As can be seen in Section 2.4, several studies have explored the impact of process variation on delay [30,147,146], power supply current [145,152,153], frequency of ring oscillators [144] and testing analog ICs [154]. Recent research has reported that process variation has a negative impact on manufacturing test quality, including the studies in [146,147,151,149,148,150] which considered the effect of process variation on delay fault testing.…”

“…It is often assumed that the transistor threshold voltage (VT) and the width (W) and length (L) of a transistor have Gaussian distributions under process variation [152]. A detailed study on the influence of dopant distribution [21] observed that the transistor threshold voltage distribution is bell-shaped like a Gaussian distribution.…”

“…A detailed study on the influence of dopant distribution [21] observed that the transistor threshold voltage distribution is bell-shaped like a Gaussian distribution. Based on these reports [152,21] and the fact that a sum of independent random variables with Gaussian distribution also has a Gaussian distribution (central limit theorem [162]), it is assumed that the logic threshold voltage variation of a gate input and the voltage on the bridged nets as resulting from gate drive strength variation both can be represented by Gaussian distributions.…”