High‐speed, high‐resolution methodology for portable universal radar target‐echo simulator

Abstract

In this paper, digital parallelization and fractional delay-based novel methods are proposed for the realization of high bandwidth, high-resolution Ku-band radar target simulator with 2.5 GHz intermediate frequency. High bandwidth waveform from radar is sampled by high-speed Analog to Digital Converter, and samples are parallelized in Field Programmable Gate Array (FPGA) to work at the nominal clock frequency. In Digital RF Memory-based target simulator, for finer range resolution, the FPGA clock frequency needs to be increased, which leads to increased system design complexity. The finer range resolution is accomplished without altering the system clock frequency using variable fractional delay filters and the digital parallelization methodology is proposed in this paper. The maximum target range that can be simulated is 20 km. As a result, memory requirements, computational complexity, and power dissipation are reduced. Finally, simulation and implementation results are presented.