High Speed High Capacity Memories for Secured Internet of Things based systems

Abstract

The Internet of Things (IoT) is a network connecting objects ranging from remote sensors to smart devices and tablets. To support high speed and high caacity networking speed the database management system (DBMS). To meet the requirements of DBMS of IoT smart micro devices are in high demand to store and access the data. Dual Edge Triggering (DET) flip-flops stand out to be a unique solution overcoming the trade-offs between speed and power. This paper presents a 64-bit register to control the flow of data to enhance the communication between devices connected over IoT. Though the concept of DET is subsisting, the design of area power and delay flipflops efficient is still under design process. In this paper two new D-type flip-flops with Dual Edge Triggering are proposed. One among the two consists of 14 Transistors (14T) and the other consists of 12 Transistors (12T). The two designs are compared with existing 16 Transistor (16T) DET Flip-Flop. 14T DETFF (Dual Edge Triggered Flip-Flop) is found to be efficient in terms of area power and delay parameters. 12T DETFF shows really amazing and efficient results than 14T. Results are derived by simulating the circuits at 45nm technology at 1.2V supply voltage. It is observed that propagation delay of 14T is reduced by 45.39% when compared with 16T, for 12T it is reduced by 60.52% with respect to 16T. For 14T decrease in area is observed to be 18.42%, and 12T 36.16% of area is reduced when compared with 16T. Examinations of Dynamic Power scattering is finished with various capacitive loads, at various frequencies for multi bit registers extended up to 64-bits.