High speed FPGA-based chaotic oscillator design

Tuna, Murat; Alçın, Murat; Koyuncu, İ̇smail; Fidan, Can Bülent; Pehlivan, İ̇hsan

doi:10.1016/j.micpro.2019.02.012

Cited by 56 publications

(29 citation statements)

References 38 publications

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“…In [90], by the help of fourth-order of RK4 method, Sundarapandian-Pehlivan chaotic system was proposed in VHDL 32-bit IEEE 754-1985 floating-point number standard on Virtex-6 FPGA chip. In [91], autonomous Lu-Chen chaotic system was implemented on Virtex-6 FPGA chip using Heun numerical algorithm in VHDL 32-bit IQ-Math fixed-point number format. In [92], with the method of Artificial Neural Networks, the design of Pehlivan-Uyaroglu chaotic system was implemented in VHDL IEEE 754 single precision floating-point number format on Virtex-6 FPGA chip.…”

Section: Complexitymentioning

confidence: 99%

“…Meanwhile, in some chaotic information systems, digital implementation may be necessary, for example, in embedded chaos-based application areas and many other chaotic digital information systems. Digital chaotic generators have been implemented by varied structures such as Digital Signal Processor (DSP) [88,89] and Field Programmable Gate Array (FPGA) [90][91][92][93][94]. In order to calculate complex mathematical operations, the DSP chips are optimized operations sequentially.…”

Section: Introductionmentioning

confidence: 99%

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CCII and FPGA Realization: A Multistable Modified Fourth-Order Autonomous Chua’s Chaotic System with Coexisting Multiple Attractors

Shen

Liu

et al. 2020

Complexity

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In this paper, a multistable modified fourth-order autonomous Chua’s chaotic system is investigated. In addition to the dynamic characteristics of the third-order Chua’s chaotic system itself, what interests us is that this modified fourth-order autonomous Chua’s chaotic system has five different types of coexisting attractors: double-scroll, single band chaotic attractor, period-4 limit cycle, period-2 limit cycle, and period-1 limit cycle. Then, an inductorless modified fourth-order autonomous Chua’s chaotic circuit is proposed. The active elements as well as the synthetic inductor employed in this circuit are designed using second-generation current conveyors (CCIIs). The reason for using CCIIs is that they have high conversion rate and operation speed, which enable the circuit to work at a higher frequency range. The Multisim simulations confirm the theoretical estimates of the performance of the proposed circuit. Finally, using RK-4 numerical algorithm of VHDL 32-bit IQ-Math floating-point number format, the inductorless modified fourth-order autonomous Chua’s chaotic system is implemented on FPGA for the development of embedded engineering applications based on chaos. The system is simulated and synthesized on Virtex-6 FPGA chip. The maximum operating frequency of modified Chua’s chaotic oscillator based on FPGA is 180.180 MHz. This study demonstrates that the hardware-based multistable modified fourth-order autonomous Chua’s chaotic system is a very good source of entropy and can be applied to various embedded systems based on chaos, including secure communication, cryptography, and random number generator.

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Section: Complexitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

CCII and FPGA Realization: A Multistable Modified Fourth-Order Autonomous Chua’s Chaotic System with Coexisting Multiple Attractors

Shen

Liu

et al. 2020

Complexity

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“…e Euler algorithm is the simplest of all algorithms, but its accuracy is not high [64,65]. e Heun algorithm is more sensitive than the Euler method [63].…”

Section: The Fpga-based Model Of the Novel 5d Hfwmsmentioning

confidence: 99%

“…erefore, researchers began to focus on digital circuits with low cost, short design cycle, fast speed, low power consumption, and high accuracy, such as digital signal processor (DSP) [61,62] and field programmable gate array (FPGA) [63][64][65][66]. It takes a long time for DSPs to generate chaotic signals at high frequencies and DSP chips to perform operations in order to calculate the value of output signals.…”

Section: Introductionmentioning

confidence: 99%

“…At present, there are several studies related to designs of chaotic systems based on FPGA. Tuna et al [63] implemented the Liu-Chen chaotic system on the Xilinx virtex-6 FPGA chip using the 32-bit IQ-Math fixed-point number Heun algorithm. Ahmadi et al [64] designed a 5D chaotic system on the Xilinx Kintex-7 KC-705 kit FPGA chip using the IEEE 754 32-bit fixed-point number Euler's method.…”

Section: Introductionmentioning

confidence: 99%

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Analysis and FPGA Realization of a Novel 5D Hyperchaotic Four‐Wing Memristive System, Active Control Synchronization, and Secure Communication Application

Liu

et al. 2019

Complexity

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By introducing a flux-controlled memristor with quadratic nonlinearity into a 4D hyperchaotic system as a feedback term, a novel 5D hyperchaotic four-wing memristive system (HFWMS) is derived in this paper. The HFWMS with multiline equilibrium and three positive Lyapunov exponents presented very complex dynamic characteristics, such as the existence of chaos, hyperchaos, limit cycles, and periods. The dynamic characteristics of the HFWMS are analyzed by using equilibria, phase portraits, poincare map, Lyapunov exponential spectrum, bifurcation diagram, and spectral entropy. Of particular interest is that this novel system can generate two-wing hyperchaotic attractor under appropriate parameters and initial conditions. Moreover, the FPGA realization of the novel 5D HFWMS is reported, which prove that the system has complex dynamic behavior. Finally, synchronization of the 5D hyperchaotic system with different structures by active control and a secure signal masking application of the HFWMS are implemented based on numerical simulations and FPGA. This research demonstrates that the hardware-based design of the 5D HFWMS can be applied to various chaos-based embedded system applications including random number generation, cryptography, and secure communication.

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