High-speed FIR-filter architectures with scalable sample rates

Vaupel, M.; Meyr, H.

doi:10.1109/iscas.1994.409207

Cited by 4 publications

(3 citation statements)

References 10 publications

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“…The number of full adder cells between two consecutive pipeline register cells has been chosen to be 2 in order to gain the smallest possible area while fulfilling the constraints on the data rate. This results in a modified structure (Vaupel & Meyr 1994) compared to (Noll 1987). The principle of the structure is depicted in Figure 3 exemplified by a filter with three taps and a coefficient word length of four bit.…”

Section: Timing Synchronizationmentioning

confidence: 99%

“…Exploiting a carry-save representation as internal data format, the filters are implemented as rows of adder cells (bitplanes). Since investigations led to an optimum pipeline depth (the number of additions between two registers) of three, a re-ordering of the bitplanes similar to (Vaupel & Meyr 1994) has been applied to reduce silicon real estate. In order to provide the adder cells with the correctly delayed values, the input samples are delayed in one shift register chain.…”

Section: Figure 4 Block Diagram Of One Branch Of the Matched Filtermentioning

confidence: 99%

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An All-Digital Single-Chip Symbol Synchronizer and Channel Decoder for DVB

Vaupel

Lambrette

Dawid

et al. 1997

VLSI: Integrated Systems on Silicon

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In this contribution, design process and implementation of a single-chip timing and carrier synchronizer and channel decoder for digital video broadcasting over satellite (DVB-S) is described. The device consists of an A-to-D-converter with AGC, timing and carrier synchronizer including matched filter, Viterbi decoder including node synchronization, byte and frame synchronizer, convolutional de-interleaver, Reed Solomon decoder, and a descrambler. The system was designed in accordance with the DVB specifications. It is able to perform Viterbi decoding at data rates up to 56 Mbit/s and to sample the analog input values with up to 88 MHz. The chip allows automatic acquisition of the convolutional code rate and the position of the puncturing mask. The synchronization to the variable sample rates is performed fully digital by means of interpolation and controlled decimation. Hence, no external analog clock recovery circuit is needed. For algorithm design, system performance evaluation, and co-verification of the building blocks an advanced design methodology was used. This guarantees both short design time and high reliability. The chip has been fabricated in a 0.5 p.m CMOS technology with three metal layers. A die photograph is presented.

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Section: Timing Synchronizationmentioning

confidence: 99%

Section: Figure 4 Block Diagram Of One Branch Of the Matched Filtermentioning

confidence: 99%

An All-Digital Single-Chip Symbol Synchronizer and Channel Decoder for DVB

Vaupel

Lambrette

Dawid

et al. 1997

VLSI: Integrated Systems on Silicon

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“…The complexity of developed generators reaches from simple logic functions or micro processor interjaces to quite complex blocks like Viterbi decoders [15], CORDIC processors [16] or filters with fixed or variable coefficients [17].…”

Section: Generator Clause I-gzr>mentioning

confidence: 99%

ComBox: library-based generation of VHDL modules

Vaupel

Grotker²,

Meyr³

VLSI Signal Processing, IX

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In this contribution we describe the automated generation of components for high throughput data-flow dominated VLSI-systems in digital communications. By means of a hierarchically organized library both behavioural models with high simulation efficiency and corresponding hardware genera tors that produce sophisticated VHDL descriptions are made easily accessible to the system designer. The structured approach allows the evaluation of the trade-offs between alternatives at each design step and guarantees a fast and reliable design flow towards hardware. The design environment ComBox enhances reusability and enables rapid implementation of complex systems starting from a system level description.

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