High speed domino logic circuit for improved performance

Shiksha,; Kashyap, Kamal Kant

doi:10.1109/sces.2014.6880112

Cited by 4 publications

(2 citation statements)

References 10 publications

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“…Another suggestion was made by Shiksha as for charge sharing. This suggestion has high speed with better performance using 90nm in OR gates biased at 1V [9]. Also details of Sang-Yun's low swing & low power circuit, which deployed using a pair of pMOS & nMOS transistor to lower the signal's amplitude, was published in 2014 [10].…”

Section: Precedent Researchesmentioning

confidence: 99%

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An efficient high speed, high frequency domino-logic based circuit

Zare

Manouchehrpour

Esmaeilkhah

2018

IJET

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As the Very Large-Scale Integration (VLSI) techniques are mostly focused on high-speed and low power consumption circuits, various techniques and technologies were investigated to gain these two precious goals. Domino-logic is one of the circuits which is regarded to have high speed, high frequency and low power consumption. This work proposes a Domini logic circuit which has improved PDP compare to the previous one. The suggested circuit was simulated and the attained results show a considerable improvement in circuit's speed in respect with its ancestor. The PDP of the circuit in 90 nm, biased at 1V, has been calculated as 53% approximately improvement. This improvement for PDP in 65 nm, 45 nm and 32 nm are 48%, 47% and 51% respectively.

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Section: Precedent Researchesmentioning

confidence: 99%

“…Figure 1 illustrates a two-input High Speed Domino-based OR gate, or simply a HSD OR gate [9]. Besides having higher resistance against leakage currents in respect with Footer and Footless Domino circuits, the proposed circuit shows higher operational speed.…”

Section: High Speed Domino Logic Circuitmentioning

confidence: 99%