High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor

Abstract

Traditionally, the advantages of compact image sensors (CISs) over CCDs have been low power consumption and the capability for system integration. Additionally, the image quality of CISs has recently begun to rival and even surpass that of CCDs in the area of high-speed imaging [1]. Compared to high-speed CCDs, CISs utilize the advantage of a column-parallel pixel readout. Column-parallel ADCs allow for low-bandwidth readouts. This is a key advantage over wide-bandwidth single-output amplifiers in CCDs or single ADC CISs. In order to realize these high-speeds, CISs need to simultaneously achieve a high-speed data rate and high image quality (equivalent to that of CCDs). A progressive 1/1.8-inch 1920×1440 CMOS image sensor with a column-inline dual-CDS architecture is designed in a 0.18µm CMOS process. This architecture implements high-speed digital sampling with analog CDS on column-parallel ADC for high-speed and highquality imaging. Random noise is 5.2erms at 180frames/s. The dynamic range at 180frames/s (corresponding to a 600MHz rate and 6.0Gb/s) is 68dB. The FPN is <0.5erms without the additional FPN-correction circuit.This CIS is composed of 6 main parts. 1) a 1920×1440 pixel array, 2) 1440 row decoders and drivers, 3) 1920 column parallel ADCs, 4) a single-slope ramp generator DAC with 12b accuracy, 5) digital logic control, and 6) a 12b LVDS interface (at a frequency of up to 600MHz). Figure 27.5.1 shows the block diagram of the whole system. The CIS operates with a single master clock at 74.25MHz. Additionally, a PLL generates a 297MHz clock, φ PLL , quadruple the master clock. This clock is supplied to the column ADCs, slope DAC, and the LVDS interface.• 2006 IEEE International Solid-State Circuits Conference 1-4244-0079-1/06 ©2006 IEEE

Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

“…Therefore, the conversion time of two-step SS-ADC is theoretically 16 times faster than that of the conventional SS-ADC. Two-step SS-ADC is suitable for high speed CIS systems [3][4][5][6][7][8]. Fig.…”

“…Among many kinds of column parallel ADCs, SingleSlope ADC (SS-ADC) is mostly adopted at each column of CIS due to its small chip area and low power consumption [1][2][3][4][5][6]. However, since the conversion speed of SS-ADC is very slow, the frame rate of CIS is also very low.…”

“…Thus it is hard to use SS-ADC at the high speed systems like HDTV and high resolution cameras to request a frame rate of 30 frames/s or more at a high resolution. In order to overcome the disadvantage of SS-ADC, many approaches have been reported [5][6][7][8][9]. Among them, cyclic ADC or Successive Approximation Register(SAR) ADC are well-known technique for the high frame rate CIS.…”

Recent progress in the technology linking sensors and digital circuits

“…When used in combination of analog CDS with a column amplifier, noise components of the pixel and the column amplifier can be removed simultaneously. The 1.77 megapixel imager with the PLL, which generates a 2.4 GHz clock signal, achieved a frame rate of 120 fps and data transfer rate of 34.8 Gbps in 2011 [17,18]. Cyclic ADCs (which repeatedly use one unit of a pipelined ADC) and SAR ADCs have also been used in high-speed column ADCs.…”

Design and Evaluation of a CMOS Image Sensor with Dual-CDS and Column-parallel SS-ADCs

“…Correlated double sampling (CDS) has been widely employed to reduce FPN due to mismatches of columns and transistors [1][2][3][4][5]. There are three types of CDS: analog CDS using the capacitors and switches in front of an analog-to-digital converter (ADC) [2,3], digital CDS with double counting of reset and readout signals [4], and dual CDS which employs both analog and digital CDS schemes [5]. The digital CDS suppresses FPN more precisely than the analog CDS, although it requires additional analog-to-digital conversion time for sensing the reset voltage.…”