High speed differential I/O overview and design challenges on Intel enterprise server platforms

Lee, Beomtaek; Mazumder, Md. Mohiuddin; Mellitz, Richard

doi:10.1109/isemc.2011.6038414

Cited by 9 publications

(2 citation statements)

References 4 publications

(2 reference statements)

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“…In this paper, it is demonstrated that, (1) the different behaviors of the conductor loss and dielectric loss of PCB is one key factor determining the performance of equalizers in high speed signaling; (2) the performance of equalizers are sensitive to the variation of total transfer function at the low-mid band frequency range, which was also shown in the literature. In the proposed technique, the optimized settings are obtained through calculating the variation of total transfer function (S 21 or S dd21 ) including channel loss, equalizers, and other contributions such as on-chip pad response (C pad ) over the low-mid frequency range.…”

Section: Introductionmentioning

confidence: 67%

Novel Broadband Equalizer Optimization Technique for High-Speed Digital System Designs

Huang¹,

Lee²

2016

PIER B

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In this paper, a novel broadband equalizer optimization technique is introduced for highspeed digital system designs. Through effectively compensating both conductor loss and dielectric loss, this technique provides a new solution to find optimal equalizer for high-speed signaling over printed circuit board (PCB) with continuous time linear equalizer (CTLE) as an application. The coefficients of CTLE are quickly identified through searching the minimum of the variation of total transfer functions over the low-mid frequency range. Channel simulations with different server interfaces of 12 Gbps and 25 Gbps are performed, respectively. Simulation results are presented to validate the technique.

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Section: Introductionmentioning

confidence: 67%

Novel Broadband Equalizer Optimization Technique for High-Speed Digital System Designs

Huang¹,

Lee²

2016

PIER B

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“…Parallel bus has reached a limit. The ever-increasing throughput requirements have forced conversion of IO buses from multi-load parallel single-end buses to point-topoint serial differential buses [6].…”

Section: Introductionmentioning

confidence: 99%

Implementation of High-Speed Serial Interconnects for Multi-Processor Parallel System

Wang

Zhao

Yang

et al. 2015

Lecture Notes in Electrical Engineering

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Abstract. Multi-processor parallel system is widely used to meet the increasing demand of high-performance computing. However, the data interacting between processors is often a bottleneck as it is hard for parallel buses to address the requirement of transmitting mass data in high speed. Based on differential signal and embedded clock technology, high-speed serial interconnect has been the ideal solution. In this paper, we designed a multi-processor parallel system and implemented the high-speed serial interconnects between processors based on Serial Rapid IO (SRIO), PCI Express (PCIe), and Hyperlink protocols. The test results are given to show the throughput performance of these interconnects.

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PCB design for signal integrity

Zhang¹,

Krooswyk²,

Ou³

2015

High Speed Digital Design

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High speed differential I/O overview and design challenges on Intel enterprise server platforms

Cited by 9 publications

References 4 publications

Novel Broadband Equalizer Optimization Technique for High-Speed Digital System Designs

Novel Broadband Equalizer Optimization Technique for High-Speed Digital System Designs

Implementation of High-Speed Serial Interconnects for Multi-Processor Parallel System

PCB design for signal integrity

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