High speed DC-DC dead time architecture

Jarvenhaara, J.K.; Herzog, Hans Georg; Sipilä, Sami; Tian, Jing; Filanovsky, I.M.; Tchamov, N.T.

doi:10.1587/elex.12.20150662

Cited by 5 publications

(1 citation statement)

References 10 publications

(12 reference statements)

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“…So, a dead-time [2,3] is inserted to the gate control signals. In order to improve the efficiency, various literatures are reported to optimize the dead-time [4,5,6,7,8,9,10]. In [6], the dead time of the power transistors can be dynamically optimized under any load condition.…”

Section: Introductionmentioning

confidence: 99%

A reliability improved synchronous boost converter with spike suppression circuit

Zhang

et al. 2015

IEICE Electron. Express

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A reliability improved synchronous boost converter with spike suppression circuit is proposed in this paper. Compared with the traditional boost converter, a novel control circuit is designed to suppress the voltage spike at node SW during the dead time. In addition, the two main power switches could be avoided to operate in ON state during the transient process. Hence, both the reliability and the efficiency are improved. The converters with/without spike suppression circuit are designed and implemented in a 0.5 µm standard CMOS processes. The experimental results show that the voltage spike at node SW is reduced 43% when the load current is 0.5 A, and the efficiency is improved at light load.

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