High speed ASIC design of complex multiplier using Vedic Mathematics

Saha, Prabir; Banerjee, Arindam; Bhattacharyya, P.; Dandapat, Anup

doi:10.1109/techsym.2011.5783852

Cited by 72 publications

(19 citation statements)

References 7 publications

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“…In paper [34], Prabir Saha, et.al, proposed a novel complex multiplier ASIC design using Vedic mathematics. The authors concluded that the design works at higher speed and can be used for various applications.…”

Section: Related Workmentioning

confidence: 99%

An Exhaustive Research Survey on Vedic ALU Design

M¹

2016

IJIRCCE

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ABSTRACT:The digital India is playing an important role nowadays. Indian Vedas and Upanishads are also important and have a great history. That too Vedic mathematics was, is and will be an important basic logic for all mathematical related applications in various fields of science and technology. VLSI is an ever growing field which involves Analog, Digital and Mixed mode Designs. Also in VLSI research, an ALU is a very important system which involves user specifications while designing, for applications like microprocessor, microcontroller, signal processing and various fields. This paper concentrates on the related work on design of Vedic ALU, till date from 46 different IEEE papers and provides some common problem statements and solutions that can be used to design the best ALU, which is not done till date. Importance of reconfigurable feature is also explained in this paper.

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Section: Related Workmentioning

confidence: 99%

An Exhaustive Research Survey on Vedic ALU Design

M¹

2016

IJIRCCE

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“…Prabir Saha et.al [3] presents report on a novel complex number multiplier design based on the formulas of the ancient Indian Vedic Mathematics, highly suitable for high speed complex arithmetic circuits. They designed complex multiplier by using parallel adders and subtractors.…”

Section: Related Workmentioning

confidence: 99%

“…PROPOSED MULTIPLIER From overall analysis of related work, it is observed that number of researchers have designed multiplier to reduce delay and power. The proposed work is to design a high Figure 2: Implementation method of complex multiplier [3] speed 32-bit single precision Floating Point Complex Multiplier using Vedic Mathematics. Many authors have designed a multiplier only for a floating point number calculation.…”

Section: Overall Analysis Of Related Workmentioning

confidence: 99%

Review of High Speed 32-bit Single Precision Floating Point Complex Multiplier using Vedic Mathematics

Kewate¹,

Indurkar²,

Hinganikar³

2016

International Journal of Innovative Research in Electrical, Ele

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Multipliers are essential component of digital signal processing as they are used for determining the speed of Digital Signal Processor (DSP). The floating point complex multiplication is one of the basic functions used in digital signal processing application, microprocessors and FIR filters. Floating point format is a standard format used almost in all processing elements. Delay and power are main parameters used to determine the speed of multiplier. Conventional multipliers require more delay and hence consume more power for the multiplication. The Vedic mathematics technique is widely used because of its fast computational ability. This paper presents a review of 32bit single precision floating point complex multiplier using Vedic mathematics and proposes a design for high speed 32 bit single precision floating point complex multiplier using Vedic mathematic.

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“…LMS algorithm is the basic adaptive algorithm available, this algorithm helps any system to mimic a desired filter by generating weights adaptively according to the value to error signal ( Figure 5) [8].…”

Section: Lmsmentioning

confidence: 99%

Implementation of LMS-ALE Filter using Vedic Algorithm

U¹

2015

J Appl Computat Math

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High speed ASIC design of complex multiplier using Vedic Mathematics

Cited by 72 publications

References 7 publications

An Exhaustive Research Survey on Vedic ALU Design

An Exhaustive Research Survey on Vedic ALU Design

Review of High Speed 32-bit Single Precision Floating Point Complex Multiplier using Vedic Mathematics

Implementation of LMS-ALE Filter using Vedic Algorithm

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