2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) 2016
DOI: 10.1109/iceeot.2016.7754768
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High speed area efficient 1-bit hybrid full adder

Sachin Kumar
1
,
Aman Kumar
2
,
Puneet Bansal
3
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Cited by 6 publications
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References 9 publications
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Performance Analysis of 16 bit Adders in high speed computing applications

Kumar1,
C2,
Karthi3
2019
2019 International Conference on Advances in Computing and Communication Engineering (ICACCE)
6
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0
0
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Performance Analysis of 16 bit Adders in high speed computing applications

Kumar1,
C2,
Karthi3
2019
2019 International Conference on Advances in Computing and Communication Engineering (ICACCE)
6
0
0
0
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Eight Bit Full Adder Design Using Fifteen Transistors With Novel Five Transistors XNOR Gate

Sritha1,
Geethamani2
2019
2019 International Conference on Advances in Computing and Communication Engineering (ICACCE)
0
0
0
0
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Low power adder using multi gate FET in 32nm technology

Shankar1,
Gupta2,
Tiwari3
et al. 2022
2022 2nd International Conference on Advance Computing and Innovative Technologies in Engineering (ICACITE)
2
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