2005 IEEE International Symposium on Circuits and Systems
DOI: 10.1109/iscas.2005.1466011
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High-Speed and Low-Power Design of Parallel Turbo Decoder

Abstract: This paper presents the high speed and low power design of a turbo decoder with parallel architecture. To solve the memory conflict problem of extrinsic information in such parallel architectures, a two-level mapping approach is proposed for designing a collision-free parallel interleaver. Since the warm-up process in the parallel architecture increases the decoding delay, a new parallel architecture without warm-up is proposed for high speed applications. The proposed parallel architecture increases decoding … Show more

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