High-speed and logic-compatible split-gate embedded flash on 28-nm low-power HKMG logic process

Lee, Yong Kyu; Jeon, Chang Ho; Min, Hyang Ki; Seo, Bong-Gun; Kim, Kwangtae; Kim, Dong-Hyun; Min, Kyungsoo; Woo, Jeong-Ho; Kang, Hyo-Soon; Chung, Y.; Kim, Minsu; Jang, Jae Hoon; Yeom, Kyongsik; Kim, Jisung; Oh, M.; Lee, Hyosang; Cho, Sunghee; Lee, Duck‐Hyung

doi:10.23919/vlsit.2017.7998171

Cited by 9 publications

(7 citation statements)

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“…Endurance is the number of times that data can be written to an NVM cell before it begins to register errors. Whereas SRAM and DRAM can effectively change memory state an I, endurance ranges from about 10 5 in modern embedded flash [6] to >10 11 in spin-transfer torque magnetic random access memory (STT-MRAM) [7]. Endurance in some technologies can also be improved or sacrificed as a tradeoff for other properties, such as reduced retention or longer program times.…”

Section: A Nvm Basicsmentioning

confidence: 99%

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Radiation Effects in Advanced and Emerging Nonvolatile Memories

Marinella

2021

IEEE Trans. Nucl. Sci.

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Despite hitting major roadblocks in 2-D scaling, NAND flash continues to scale in the vertical direction and dominate the commercial nonvolatile memory market. However, several emerging nonvolatile technologies are under development by major commercial foundries or are already in small volume production, motivated by storage-class memory and embedded application drivers. These include spin-transfer torque magnetic random access memory (STT-MRAM), resistive random access memory (ReRAM), phase change random access memory (PCRAM), and conductive bridge random access memory (CBRAM). Emerging memories have improved resilience to radiation effects compared to flash, which is based on storing charge, and hence may offer an expanded selection from which radiation-tolerant system designers can choose from in the future. This review discusses the material and device physics, fabrication, operational principles, and commercial status of scaled 2-D flash, 3-D flash, and emerging memory technologies. Radiation effects relevant to each of these memories are described, including the physics of and errors caused by total ionizing dose, displacement damage, and single-event effects, with an eye toward the future role of emerging technologies in radiation environments.

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Section: A Nvm Basicsmentioning

confidence: 99%

“…Resistance change memories typically demonstrate very fast switching at the cell level (<10 ns), but have slower array access times, due to array circuitry and error correction. A comparison of key properties of embedded DRAM (eDRAM) and major embedded NVM technologies is given in Table I (values from [6]- [12] and references therein).…”

Section: A Nvm Basicsmentioning

confidence: 99%

Radiation Effects in Advanced and Emerging Nonvolatile Memories

Marinella

2021

IEEE Trans. Nucl. Sci.

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“…A 14-/16-nm process was modeled for the digital logic and interconnects. We assume that the SONOS cell can scale to 28 nm and estimate a gate capacitance of 100 aF and cell area of 0.053 µm 2 based on existing 28-nm floating-gate transistors [13], [14]. We also assume that it is possible to optimize the channel to give the high resistance (100 M ) needed for large-scale arrays.…”

Section: Architectural Evaluationmentioning

confidence: 99%

Using Floating-Gate Memory to Train Ideal Accuracy Neural Networks

Agarwal

Garland

Niroula

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Floating-gate silicon-oxygen-nitrogen-oxygen-silicon (SONOS) transistors can be used to train neural networks to ideal accuracies that match those of floating-point digital weights on the MNIST handwritten digit data set when using multiple devices to represent a weight or within 1% of ideal accuracy when using a single device. This is enabled by operating devices in the subthreshold regime, where they exhibit symmetric write nonlinearities. A neural training accelerator core based on SONOS with a single device per weight would increase energy efficiency by 120×, operate 2.1× faster, and require 5× lower area than an optimized SRAM-based ASIC.

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“…However, required voltages are higher on the diode selector but still remain compatible with embedded memory specifications. As compared to other technologies, a PCM cell with a diode on FD-SOI would benefit from smaller dimensions than recently published BEOL or Flash eNVM memories in 28nm [6,7].…”

Section: Process and Electric Simulations To Improve Performances mentioning

confidence: 99%

Low Cost Diode as Selector Device for Embedded Phase Change Memory in Advanced FD-SOI Technology

Fagot¹,

Boivin²,

Della-Marca³

et al. 2018

2018 IEEE International Memory Workshop (IMW)

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This paper presents a new diode selector for embedded Phase Change Memory (PCM) in advanced FD-SOI technology. It has been developed to achieve a very low cost selector device but still very efficient to meet PCM specifications. This new device takes all advantages of CMOS in FD-SOI: buried oxide (BOX), shallow trench isolation (STI) and high k metal gates to allow very low leakages between cells, thus offering great potential for designing embedded memory arrays of up to several Mbit. The selector can drive 300µA at 2V through the memory cell with 2.5V applied on gates together with a limited leakage current of less than 10pA/cell. The effective cell area of under 0.025µm² is very competitive as compared to a MOS selector, offering a size reduction of around 60% for the same driving current. Therefore, the new diode on FD-SOI devices is a great solution for a PCM selector due to its very low cost and high density.

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High-speed and logic-compatible split-gate embedded flash on 28-nm low-power HKMG logic process

Cited by 9 publications

References 0 publications

Radiation Effects in Advanced and Emerging Nonvolatile Memories

Radiation Effects in Advanced and Emerging Nonvolatile Memories

Using Floating-Gate Memory to Train Ideal Accuracy Neural Networks

Low Cost Diode as Selector Device for Embedded Phase Change Memory in Advanced FD-SOI Technology

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