High-speed and energy-efficient subthreshold level converter for wider voltage conversion

Arulkarthick, V J; Saravanakumar, R.; Chakrapani, Arvind; Kannan, Srihari

doi:10.1007/s10470-021-01977-x

Cited by 1 publication

(2 citation statements)

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“…Similarly, usage of two stage cross coupled LS [13], combination of CM LS and crosscoupled LS in two stages [14], regulated pull-up [15] and usage of multi-threshold devices [16] are also provides better solution to CC with larger propagation delay. In [17,18], hybrid pull up network is used to suppress the pull-up current while the pull-down network is activated. The abovementioned solutions addresses the issue of CC with penalty of higher delay and larger area with circuit complexity.…”

Section: Introductionmentioning

confidence: 99%

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Fast and Ultra-Low Energy Subthreshold Level Shifter using Split-gate Buffer for Low-power Digital VLSI Systems

SA¹,

Senthilkumar²,

Saravanakumar

2022

Preprint

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Low-energy operation is predominant feature in the modern wireless sensor node and implantable biomedical applications. Scaling the supply voltage towards sub-/near-threshold level is vital design methodology to achieve energy-efficient operation. Voltage scaling can be adopted in the multiple supply voltage design incorporating interfacing circuit called voltage level shifters to achieve power-efficient operation. This paper presents differential cascode voltage switch (DCVS) structure based high-speed and low-energy voltage level shifter for converting subthreshold voltage to nominal output voltage. The proposed level shifter (LS) utilizes NMOS/PMOS diode pairs along with the cross-coupled PMOS to address the current contention issue by suppressing the current from pull-up network while pull-down network is activated. The switching speed of the level conversion is enhanced by pass transistor and boosting devices in the pull-down network. Further, split-gate inverter/buffer at the output stage ensures high performance by alleviating static power and accelerating speed performance. The proposed LS is implemented in CMOS 180nm technology on Cadence (Virtuoso) platform and analyzed using Spectre circuit simulator. The simulation results reveal the subthreshold level conversion from 220 mV to 1.8 V and wider frequency range of conversion. In addition, it ensures the delay of 8.57 ns, energy/transition of 39.4 fJ for level conversion from 0.4 V to 1.8 V with input signal frequency of 1 MHz. Moreover, the LS consumes static power of 0.302 nW at standby mode.

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Section: Introductionmentioning

confidence: 99%

“…1d. Many researchers suggested different solutions to diminish issue of CC [ [4] - [18]]. Increased device size of the pulldown network to dominate the pull-up devices [10] and reducing strength of pull-up network [11,12] limit the CC considerably with larger area.…”

Section: Introductionmentioning

confidence: 99%