High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

Abstract

In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power-delay product was the lowest among the structures considered in this paper, while its energy-delay product was almost the same as that of the Kogge-Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed.Index Terms-Carry skip adder (CSKA), energy efficient, high performance, hybrid variable latency adders, voltage scaling.

Analysis of Low Power High Speed Carry Skip Adder: A Review

“…In addition, AOI and OAI compound gates were exploited for the carry skip logics. [1] The critical path delay of the CSKA is much smaller than the one in the RCA, whereas its area and power consumption are similar to those of the RCA. In addition, the power-delay product (PDP) of the CSKA is smaller than those of the CSLA and PPA structures [1].…”

“…[1] The critical path delay of the CSKA is much smaller than the one in the RCA, whereas its area and power consumption are similar to those of the RCA. In addition, the power-delay product (PDP) of the CSKA is smaller than those of the CSLA and PPA structures [1]. The paper [2] entitled, the performance parameters of delay, average power, PDP and EDP are compared at different technology node.…”

“…On the other hand adder designs include the conditional sum adder, carry skip adder, and carry complete adder. In carry look-ahead architecture instead of rippling the carry through all stages (bits) of the adder, it calculates all carrys in parallel based on equation (1). Ci = gi + piCi-1…”

“…The RCA blocks are connected to each other through 2:1 multiplexers, which can be placed into one or more level structures. The CSKA configuration (i.e., the number of the FAs per stage) has a great impact on the speed of this type of adder [1]. A CSKA performs fast addition since adders are split in blocks of N bits.…”

High speed and low power Hybrid carry skip adder using DMFA

“…The dual mode full adders (DMFA) are used in Hyb-CSKA to replace the Ripple carry adders which will reduce the power consumption than other proposed structures. The proposed hybrid carry skip adders are assessing by compare with their speed, delay and energy parameters with other adders [2].…”