High-speed &amp;amp; memory efficient 2-D DWT on Xilinx Spartan3A DSP using scalable polyphase structure with DA for JPEG2000 standard

Tewari, Gaurav; Sardar, Santu; Babu, K. Ananda

doi:10.1109/icectech.2011.5941577

Cited by 9 publications

(3 citation statements)

References 13 publications

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“…In the proposed architecture is better than other architecture in shown the Table 2. [2] 43 0 9 6 TA Martina et al [5] 27 0 9 6 TA Martina et al [6] 19 8 9 6 TA Gaurav et al [7] 15 40 9 6 TA Proposed 29 0 27 6 TA  Xilinx Simulation Implementation the Gourav et al [5] and proposed architecture has been captured by VHDL and the functionality is verified by RTL and gate level simulation. Comparisons of DA based architecture and NEDA based architecture for 9/7 wavelet filter in show the Table 3.…”

Section: Simulation Resultsmentioning

confidence: 99%

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High Speed and Time Efficient 1-D DWT on Xilinx Virtex4 DWT Using 9/7 Filter Based NEDA Technique

Gupta¹,

Singh²

2013

IOSR-JCE

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In this paper, we describe an efficient Xilinx Virtix4 discrete wavelet transform (DWT) using 9/7 filter based new efficient distributed arithmetic (NEDA) Technique. We demonstrate that NEDA is a very efficient architecture with adders as the main component and free of ROM, multiplication, and subtraction. This technique supports any size of image pixel value and any level of decomposition. The bit-parallel structure has 100% hardware utilization efficiency. Compared with the existing multiplier-less structures, the proposed structures offer significantly higher throughput rate and involve less area-delay product.

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Section: Simulation Resultsmentioning

confidence: 99%

“…By that approach, they have significantly reduced the adder-complexity of the 9/7 DWT. Gourav et al [7] have suggested an LUTless DA-based design for the implementation of 1-D DWT. They have eliminated the ROM cells required by the DA-based structures at the cost of additional adders and multiplexors.…”

Section: Introductionmentioning

confidence: 99%

High Speed and Time Efficient 1-D DWT on Xilinx Virtex4 DWT Using 9/7 Filter Based NEDA Technique

Gupta¹,

Singh²

2013

IOSR-JCE

View full text Add to dashboard Cite

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“…The adder complexity of this structure is significantly higher than the other multiplier-less structures [4]. Gaurav Tewariet al [10] has proposed scalable Polyphase Structure with DA for JPEG2000, and achieved 129.8 MHz speed. In [11] the Filter coefficients of the biorthogonal 9/7-5/3 wavelet low-pass filter are quantized before implementation in the high speed…”

Section: Introductionmentioning

confidence: 99%