High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

Metrology (including Materials Characterization) for Nanoelectronics

“…Modeling provides an understanding of how compressive stress along the <110> direction of silicon increases hole mobility [14,15]. Unfortunately, direct measurement of the localized stress in a buried channel is very difficult.…”

“…Electron mobility in nMOS transistors has been improved through the tensile stress induced by silicon nitride films above the transistor [14,15,17]. Different approaches have been used to compressively stress the channel of PMOS [14,15]. Intel creates compressive stress by removing the source and drain and replacing the doped silicon with silicon germanium.…”

“…Intel's now famous transistor crosssections of this process are shown in Figure 4. IBM's process uses the distance between the shallow trench isolation and the transistor gate as a means of increasing or decreasing the channel stress for pMOS [15]. According to Intel's public WEB site, improved stress engineering is used to increase I dsat in the 65 nm node microprocessors being used in the 65 nm node.…”

“…The first high volume ICs with channel engineering appeared at the 90 nm node [14][15][16][17][18]. a variety of processes were used to improve electron and hole mobility.…”

An open-source platform to study uniaxial stress effects on nanoscale devices

“…This effect has been used to enhance the performance of complementary metal oxide semiconductor (CMOS) field-effect transistors and to advance optoelectronic devices based on III-V alloys. [3][4][5][6][7][8][9][10] Semiconducting nanostructures also exhibit interesting mechanical properties when their lateral dimension are scaled below 100 nm. 11 Because of the competition between atomic coordination and electronic distribution, surfaces can be softer or harder than the bulk.…”