High Resolution Pulse Width Modulators in FPGA

Castro, Ángel de; Sutter, Gustavo; Huerta, Santa C.; Cobos, J.A.

doi:10.1109/spl.2007.371737

Cited by 11 publications

(9 citation statements)

References 11 publications

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“…of the advantage of this is that a high clock frequency can be internally used in the DPWM, while an external lower frequency is generated and also used in the rest of the digital controller. DLL based clock multiplication is used in the DPWM as reported in [45,48,49]. As shown in Figure 8a, a 32 MHz external clock is multiplied by 4 for a 128 MHz internal clock in the DPWM.…”

Section: Fpga Resources: Delay-locked Loop (Dll)mentioning

confidence: 99%

“…Most DLLs in FPGAs also generate phase-shifted versions of the output clock. The clock shifting feature allows multiplication of time resolution by 4 (2-additional bits) beyond the maximum resolution achievable with a counter-based technique [45,48]. The DPWM could obtain a higher resolution, multiplying the resolution of a counter-based solution by the number of available clocks.…”

Section: Fpga Resources: Delay-locked Loop (Dll)mentioning

confidence: 99%

“…As shown in Figure 8b, the Synchronous block is based on a counter and comparison structure; capable of working at high clock frequencies due to its simplicity. In the synchronous block, resolution is given by both the clock and the switching frequency, obtained as [45,48,49]:…”

Section: Synchronous Blockmentioning

confidence: 99%

“…These signals obtain four possible switching instants during each clock cycle, thus, resolution is quadrupled. In general, using m asynchronous bits (and 2 phase-shifted clocks), the total resolution is calculated as [45,48,49]:…”

Section: Asynchronous Blockmentioning

confidence: 99%

“…DPWM shown in Figure 8b [45,48,49] is formed by two blocks: a synchronous block and an asynchronous block, as already explained. The output of the synchronous block (counter-based with external frequency multiplied by 4) sets the HSM or output of the DPWM depending on the MSBs of [ ].…”

Section: Functionality Of the Hybrid Dpwm Architecturementioning

confidence: 99%

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ASIC and FPGA based DPWM architectures for single-phase and single-output DC-DC converter: a review

Chander¹,

Agarwal

Gupta

2013

Open Engineering

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Pulse width modulation (PWM) has been widely used in power converter control. This paper presents a review of architectures of the Digital Pulse Width Modulators (DPWM) targeting digital control of switching DC-DC converters. An attempt is made to review the reported architectures with emphasis on the ASIC and FPGA implementations in single phase and single-output DC-DC converters. Recent architectures using FPGA's advanced resources for achieving the resolution higher than classical methods have also been discussed. The merits and demerits of different architectures, and their relative comparative performance, are also presented. The Authors intention is to uncover the groundwork and the related references through this review for the benefit of readers and researchers targeting different DPWM architectures for the DC-DC converters.

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Section: Fpga Resources: Delay-locked Loop (Dll)mentioning

confidence: 99%

Section: Fpga Resources: Delay-locked Loop (Dll)mentioning

confidence: 99%