High Quality Testing of Grid Style Power Gating

Abstract

Abstract-This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network (VPDN). To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order to constitute the proper interface between the VPDN and the DFT. The proposed logic can be easily implemented on-top of existing DFT solutions and its overhead is optimized by an algorithm that offers trade-off flexibility between test-application-time and hardware overhead. Through physical layout SPICE simulations, we show complete fault coverage recovery on stuck-open faults and 43.2% testapplication-time improvement compared to a previously proposed DFT technique. To the best of our knowledge, this paper presents the first analysis of the VPDN impact on test quality.

Diagnosis of power switches with power-distribution-network consideration

“…Power switches testing for stuck-open faults is performed by clustering the power switches in m segments-under-test (SUTs) of segment-size L power switches [6], [16]. [16] delay-based testing against stuck-open faults on header power switches that considers a distributed PDN model (Figure 1(a)).…”

“…There are several DFT solutions to test power switches against stuck-opens [5], [6], [8], [10], [11], [16], [18], [19]. However, it was shown in [16] that they suffer from test quality loss, because they rely on a lumped model for the power-distribution-network (PDN) without considering its distributed nature. A PDNaware manufacturing testing method was proposed in [16].…”

“…However, it was shown in [16] that they suffer from test quality loss, because they rely on a lumped model for the power-distribution-network (PDN) without considering its distributed nature. A PDNaware manufacturing testing method was proposed in [16]. However, that method provides only a pass/fail test response and not any signature information related to the defect magnitude that caused the failure.…”

“…Section II reviews the state-of-the-art PDN-aware manufacturing testing method [16] and highlights its limited diagnostic capabilities. Section III analyses the diagnosis quality loss of a PDN-unaware diagnosis method [10], when it performs in a distributed PDN environment and shows that they can reach up to 67% on accuracy loss and up to 63% on resolution loss.…”

DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test

“…It was shown in [16] that, at the grid style power gating, this simplification interacts with the test result and in [17] that could even influence the diagnosis result. In Section II, we consider a distributed model for the RC components of the supply voltage PDN (SPDN), the ground voltage PDN (GPDN) and the virtual voltage PDN (VPDN).…”