High quality SiO/sub 2//Si interfaces of poly-crystalline silicon thin film transistors by annealing in wet atmosphere

Sano, Naoki; Sekiya, M.; Hara, Masaki; Kohno, Atsushi; Sameshima, Toshiyuki

doi:10.1109/55.382225

Cited by 53 publications

(21 citation statements)

References 10 publications

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“…Water vapor annealing has been shown to improve the reliability and interfacial properties of plasma-assisted oxide films on both Si and Si-Ge substrates. 23,24 In the case of our oxide films, however, while some improvements were seen in the case of Si substrates, performing water vapor anneals on oxide films deposited on Si-Ge substrates led to a significant deterioration in both the interfacial and bulk properties. This is illustrated in Fig.…”

Section: B Reliability and Annealingmentioning

confidence: 81%

Properties of gate quality silicon dioxide films deposited on Si–Ge using remote plasma-enhanced chemical vapor deposition with no preoxidation

Sharma

Fretwell

Ngai

et al. 1999

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Section: B Reliability and Annealingmentioning

confidence: 81%

Properties of gate quality silicon dioxide films deposited on Si–Ge using remote plasma-enhanced chemical vapor deposition with no preoxidation

Sharma

Fretwell

Ngai

et al. 1999

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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“…[22][23][24] First, an amorphous-Si film is deposited using lowpressure chemical-vapor deposition (LPCVD) of Si 2 H 6 . This film is then crystallized using a XeCl excimer pulsed laser, and subsequently is patterned using photolithography and chemical dry etching (CDE) by CF 4 and O 2 to form poly-Si films.…”

Section: Micro Poly-si Hall Devicesmentioning

confidence: 99%

Analysis of the Hall Effect in Micro Poly-Si Hall Devices and Origin of Offset Voltages

Yamaguchi¹,

Hashimoto²,

Segawa³

et al. 2011

Electrochem. Solid-State Lett.

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The Hall effects in micro poly-Si Hall devices with lightly-and heavily-doped n-and p-type channels are analyzed. Although the Hall voltage (V H ) has an offset voltage (V O ) even when the magnetic field (B) is zero, a normal V H occurs and its change is proportional to B. Lightly-doped n-type channels exhibit the highest sensitivity. Moreover, the polarities of V H when the polarities of B and the control current (I) are reversed are investigated. V O originates from the zigzag paths of I. The results indicate that poly-Si films can be evaluated based on the Hall effect and suggest the possibility of area sensors.Thin-film devices, which are expected to be extensively used for giant-micro electronics, allow a wide variety of advanced devices to be economically fabricated on large substrates in stacked structures. 1 In particular, poly-Si thin-film transistors (TFTs) 2 have been applied to not only flat-panel displays (FPDs) such as liquid-crystal displays (LCDs), 3 organic light-emitting diode displays (OLEDs), 4 and electronic papers (EPs), 5 but also to photosensing devices such as ambient light sensors, 6 image scanners 7 and artificial retinas. 8 Moreover, thin-film devices show promise for general electronics, including information processing. 9 The Hall effect has conventionally been utilized to evaluate material properties such as carrier density and carrier mobility, and it has also been applied to poly-Si films. 10-15 However, the Hall effect in poly-Si films has not sufficiently been analyzed, and whether an anomalous Hall effect in random systems occurs, which often appears in amorphous and polycrystalline semiconductors, 16,17 should be determined. Moreover, only an average value over a large area can be obtained using conventional millimeter-sized poly-Si Hall devices.Magnetic sensors have widely been utilized in the fields of fundamental physics, engineering, industry, medical science, etc., but conventional Gauss meters 18 and discrete parts 19 can only detect a magnetic field where a sensing device is located. Therefore, a magnetic sensor using poly-Si Hall devices has recently been proposed. 20 They can be economically fabricated on large substrates along with amplifying circuits and operating units integrated using poly-Si TFTs. However, some important performance issues such as the miniaturization limit of poly-Si Hall devices and characteristic deviation, which is a critical for area sensor applications, have yet to be sufficiently analyzed.As a follow-up to a brief letter, 21 herein the Hall effects in micro poly-Si Hall devices with lightly and heavily doped n-type channels and heavily doped p-type channels are analyzed to investigate the Hall effect in poly-Si films and to evaluate the feasibility as magnetic sensors. Moreover, the polarities of the Hall voltages when the polarities of the magnetic field and the control current are reversed are investigated. The obtained results indicate that material evaluation based on the Hall effect is suitable for poly-Si films, suggesting the potent...

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“…The trap densities at the front and back oxide interfaces of poly-Si TFT improved by plasma treatment and vapor heat treatment are extracted [9]. These treatments are well known as treatments for improving the transistor characteristics of poly-Si TFTs [10][11][12]. Poly-Si TFTs are fabricated on heavily doped silicon wafers and the heavily doped silicon wafers are used as back gate electrodes.…”

Section: Extraction Of the Trap Densities At The Front And Back Oxidementioning

confidence: 99%

Evaluation of trap states at front and back oxide interfaces and grain boundaries using electrical characteristic analysis and device simulation of polycrystalline silicon thin‐film transistors

Kimura

2005

Electron Comm Jpn Pt II

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SUMMARYThe trap states at the front and back oxide interfaces and grain boundaries of polycrystalline silicon thin-film transistors are evaluated by using electrical characteristic analysis and device simulation. First, the method for extracting the trap densities of the front and back oxide interfaces and the grain boundaries is explained as the electrical characteristic analysis. When applied to the diagnosis of actual transistor characteristics, we see that oxygen plasma treatment or vapor heat treatment effectively decreases the trap densities at the front and back oxide interfaces, and self-heating degradation increases the trap densities at the front and back oxide interfaces. Next, we use device simulation to examine the dependence of the transistor characteristics on the trap densities. When the simulation results were similarly applied to the diagnosis of actual transistor characteristics, we see that the oxygen plasma treatment naturally reduced the trap densities at the oxide interfaces, and the plasma-enhanced chemical-vapor deposition of tetraethylorthosilicate increased the trap densities at the grain boundaries. In a systematic summary of these analysis results, the effects of the trap states on the transistor characteristics, the improvement method, and the causes of degradation are discussed.

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High quality SiO/sub 2//Si interfaces of poly-crystalline silicon thin film transistors by annealing in wet atmosphere

Cited by 53 publications

References 10 publications

Properties of gate quality silicon dioxide films deposited on Si–Ge using remote plasma-enhanced chemical vapor deposition with no preoxidation

Properties of gate quality silicon dioxide films deposited on Si–Ge using remote plasma-enhanced chemical vapor deposition with no preoxidation

Analysis of the Hall Effect in Micro Poly-Si Hall Devices and Origin of Offset Voltages

Evaluation of trap states at front and back oxide interfaces and grain boundaries using electrical characteristic analysis and device simulation of polycrystalline silicon thin‐film transistors

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