High-quality epitaxial foils, obtained by a layer transfer process, for integration in back-contacted solar cells processed on glass

Effective lifetimes exceeding 300 μs in gettered p-type epitaxial kerfless silicon for photovoltaics

“…3,13 Epitaxial silicon is grown atop a porous release bilayer at an average rate of >4 lm/min, 3,14 with a low structural defect density of approximately 10 4 cm 2 . [15][16][17] The epi silicon is exfoliated, leaving a single-crystal kerfless c-Si wafer and reusable substrate (over 50 cycles demonstrated). 3,14 Epi kerfless silicon may offer additional performance advantages, such as repeatable n-and p-type doping that is tunable through the wafer thickness.…”

“…3,14 Epi kerfless silicon may offer additional performance advantages, such as repeatable n-and p-type doping that is tunable through the wafer thickness. 17 Solar cell efficiency results up to 20.6% have been reported with epi silicon; 18 however, the maximum reported effective lifetimes (s eff ) of approximately 150 ls, on n-type wafers, 19 may limit device efficiency. Even for thin wafers, s bulk requirements increase for high-efficiency devices.…”

Kerfless layer-transfer of thin epitaxial silicon foils using novel multiple layer porous silicon stacks with near 100% detachment yield and large minority carrier diffusion lengths

“…Firstly, a stack of porous silicon is electrochemically-etched on the surface of a highly boron-doped wafer in a HF-based electrolyte. The standard porous silicon stack used today is a double layer of 250-300 nm-thick high porosity detachment layer (HP-DL) underneath a 1-2 mm-thick low porosity template layer (LP-TL) [8][9][10]. After etching, the sample is annealed at a high temperature ( Z1100 1C) in hydrogen ambient [4,9,10], which results in the sintering of porous silicon leading to the formation of a detachment plane in the HP-DL and a well-closed LP-TL surface suitable for the following in-situ epitaxial growth of silicon.…”

“…The standard porous silicon stack used today is a double layer of 250-300 nm-thick high porosity detachment layer (HP-DL) underneath a 1-2 mm-thick low porosity template layer (LP-TL) [8][9][10]. After etching, the sample is annealed at a high temperature ( Z1100 1C) in hydrogen ambient [4,9,10], which results in the sintering of porous silicon leading to the formation of a detachment plane in the HP-DL and a well-closed LP-TL surface suitable for the following in-situ epitaxial growth of silicon. Note that the detachment layer (DL) and the template layer (TL) have also been called as the separation layer and starting layer, respectively, in literature [8,11].…”

Resistance and passivation of metal contacts using n-type amorphous Si for Si solar cells

“…The process flow of this novel module concept is described in more detail in previous publications. 4,5 In short, thin n-doped wafers with front side texturing and ARC (anti-reflective coating) layers, and at the back a blanket B-diffused c-Si emitter are bonded to glass by a silicone layer. Patterning of the emitter, deposition, and patterning of the i/n þ a-Si BSF (back-surface-field) contact and metallization are all performed on module level when semi-processed cells are attached to the glass front sheet.…”