High Precision Binary Coded Decimal (BCD) unit for 128-bit addition

Issa, Bayadir A.; AL-Furati, Israa S.

doi:10.1109/icecce49384.2020.9179331

Cited by 2 publications

(1 citation statement)

References 7 publications

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“…DNA was used in the computations in the recent past [1]. The very high speed integrated circuit (VHSIC) hardware description language (VHDL) is another technique utilized in this domain [2], [3]. Today one of the most important techniques of soft computing is artificial neural networks, which have been researched, studied and applied on a large scale during the last two decades.…”

Section: Introductionmentioning

confidence: 99%

Implementation three-step algorithm based on signed digit number system by using neural network

Thabit¹,

Dawood²,

Issa³

2021

IJEECS

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The need for a simple and effective system that works with high efficiency features such as high processing speed, the ability to solve problems by learning method and accomplish the largest amount of data processing accurately and in little time produces that system, which attracted the efforts of the researcher to employ neural networks in computing away from the complexities that burden traditional computers. We presented a model for the design of the arithmetic circuit for the process of addition the sign digit numbers in a new way to deal with the arithmetic operations, which employment of the use of neural networks, this model includes a theoretical and practical simulation of them. The model relied on the implementation of the addition process based on a three-step algorithm adopted by the signed systems. Which is characterized by the possibility of execution in a parallel way, and therefore it provides the advantage of completion of arithmetic operation regardless of the length of their operands, or in other words, whatever the number of bits in the operands. The simulation of the model is done by entering operands for 6 addition operations (each one has operands are 15-bit length) to be executed simultaneously.

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Section: Introductionmentioning

confidence: 99%

Implementation three-step algorithm based on signed digit number system by using neural network

Thabit¹,

Dawood²,

Issa³

2021

IJEECS

Self Cite

View full text Add to dashboard Cite

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Performance Analysis of High Speed and Low Power Binary Adders

Bhati

Sharma

Nag

2022

IOP Conf. Ser.: Mater. Sci. Eng.

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In all the arithmetic operations, addition is one of the most important and initial operations used in most of the mathematical equations. The operation is performed by many adders present in the digital world. These adders give us carries with preferred delay and power. The three main features like structure, logic, and compact circuit layout help design a better adder. This Paper aims to analyse and compare various additions for high-speed, low-power and fast calculation. The various adder designs seen in digital signal processing applications require computationally efficient adding and cumulative operations, so blocks with the required attributes must be carefully selected. Various techniques have been proposed to design efficient adders in terms of performance, low power consumption and area. This work focused on 16-bit implementations of highly optimized area-efficient Ripple Carry Adders (RCA) and Look Ahead Carry Adders (LAC), and carry select Adder. Finally, we can prove that the Carry look ahead Adder is very fast in all existing designs. These processes are simulated and synthesized in all ISE Xilinx 14.7 software.

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High Precision Binary Coded Decimal (BCD) unit for 128-bit addition

Cited by 2 publications

References 7 publications

Implementation three-step algorithm based on signed digit number system by using neural network

Implementation three-step algorithm based on signed digit number system by using neural network

Performance Analysis of High Speed and Low Power Binary Adders

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