High-performance vertically stacked bottom-gate and top-gate polycrystalline silicon thin-film transistors for three-dimensional integrated circuits

Lee, I-Che; Tsai, Tsung-Che; Tsai, Chieh Chih; Yang, Po‐Yu; Wang, Chao-Lung; Cheng, Huang–Chung

doi:10.1016/j.sse.2012.05.016

Cited by 7 publications

(9 citation statements)

References 22 publications

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“…The proposed device designed with a fin-shaped structure to increase the storage area where h accumulated and to improve the retention time. Figure 1b Figure 2 shows the key fabrication steps of the proposed 1T-DRAM based o poly-Si dual-gate MOSFET with a fin-shaped structure crystallized via excimer l crystallization consisting of a total of 11 steps [23]. First, metal is deposited on oxidized silicon wafer, and then dry etching is performed to form a bottom electrode.…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

“…First, metal is deposited on oxidized silicon wafer, and then dry etching is performed to form a bottom electrode. Second, after depositing SiO2 serving as a spacer, dry etching of the SiO2 in Figure 2 shows the key fabrication steps of the proposed 1T-DRAM based on a poly-Si dual-gate MOSFET with a fin-shaped structure crystallized via excimer laser crystallization consisting of a total of 11 steps [23]. First, metal is deposited on an oxidized silicon wafer, and then dry etching is performed to form a bottom gate electrode.…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

“…Tenth, the source and drain metal is deposited. Finally, after removing SiO 2 from the top of the electrode, SiO 2 is deposited for passivation [23].…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

“…Figure 2. Key fabrication steps of proposed 1T-DRAM based on a poly-Si dual-gate MOSFET with a fin-shaped structure crystallized via excimer laser crystallization [23].…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

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Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure

Lee

Park

et al. 2022

Nanomaterials

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In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 μA/μm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future.

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Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

“…Tenth, the source and drain metal is deposited. Finally, after removing SiO 2 from the top of the electrode, SiO 2 is deposited for passivation [23].…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

“…Figure 2. Key fabrication steps of proposed 1T-DRAM based on a poly-Si dual-gate MOSFET with a fin-shaped structure crystallized via excimer laser crystallization [23].…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

See 2 more Smart Citations

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure

Lee

Park

et al. 2022

Nanomaterials

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“…ELC can solve the thermal budget issues, however, it cannot solve the random distribution of the GBs. Because they randomly varied depending on the laser irradiation energy density 10 . The GBs are important in transistors made of poly-Si because they directly affect the transistor’s electrical performances.…”

Section: Introductionmentioning

confidence: 99%

3-D stacked polycrystalline-silicon-MOSFET-based capacitorless DRAM with superior immunity to grain-boundary’s influence

Lee

Park

Min

et al. 2022

Sci Rep

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In this paper, a capacitorless one-transistor dynamic random access memory (1 T-DRAM) based on a polycrystalline silicon (poly-Si) metal-oxide-semiconductor field-effect transistor with the asymmetric dual-gate (ADG) structure is designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film was used within the device due to its low fabrication cost and feasibility in high-density three-dimensional (3-D) memory arrays. We studied the transfer characteristics and memory performances of the single-layer ADG 1 T-DRAMs and the 3-D stacked ADG 1 T-DRAMs and analyze the reliability depending on the location and the number of grain-boundaries (GBs). The relative standard deviation (RSD) of the threshold voltages (Vth) is depending on the location and the number of GBs. The RSDs of the single-layer ADG 1 T-DRAM and the 3-D stacked ADG 1 T-DRAM are 1.58% and 0.68%, respectively. The RSDs of retention time representing the memory performances are 54.7% and 41%, respectively. As a result of the 3-D stacked structure, the averaging effect occurs, which greatly aids in improving the reliability of the memory performances as well as the transfer characteristics of 1 T-DRAMs depending on the influence of GBs. The proposed 3-D stacked ADG 1 T-DRAM helps implement a high-reliability single-cell memory device.

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A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance

Yoon

Seo

Cho

et al. 2019

Applied Physics Letters

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A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier effects. The program/erase operation of the 1T-DRAM is performed by trapping/detrapping charges in GB traps. The trapped charges cause variations in the grain energy barrier of the storage region, which forms the sensing margin of the 1T-DRAM. The proposed cell achieved a high sensing margin of 4.45 μA/μm and a long retention time (>100 ms) at a high temperature of 373 K (100 °C).

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High-performance vertically stacked bottom-gate and top-gate polycrystalline silicon thin-film transistors for three-dimensional integrated circuits

Cited by 7 publications

References 22 publications

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure

3-D stacked polycrystalline-silicon-MOSFET-based capacitorless DRAM with superior immunity to grain-boundary’s influence

A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance

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