High-performance vertical interconnection for high-density 3D chip stacking package

Umemoto, Mitsuo; Tanida, Kazumasa; Nemoto, Y.; Hoshino, Masataka; Kojima, K.; Shirai, Y.; Takahashi, Kenji

doi:10.1109/ectc.2004.1319402

Cited by 62 publications

(36 citation statements)

References 8 publications

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“…Self-oscillations circuit model for equivalent signal delay. (a) Single chip structure; (b) triple chip structure [28]. Fig.…”

Section: Discussionmentioning

confidence: 97%

“…A temperature cycle test (-40 to 125 °C) for a 4-chip stacked device constructed with Cu-Sn junction was performed for 1000 cycles. No damage was found, indicating that the fabrication technique has already reached a practically reliable level [28].…”

Section: Evaluation Of Stacked Modulesmentioning

confidence: 98%

“…For this purpose, various connection materials and fabrication techniques were investigated. It was finally verified that Au-Au ultrasonic flip-chip bonding (UFB) [25,26] and Cu-Sn connection [27,28] are techniques that meet the above requirements, as shown in Table 1.…”

Section: Stacking Integrationmentioning

confidence: 99%

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Trends and opportunities of system-in-a-package and three-dimensional integration

Bonkohara

Takahashi

Ishino

2005

Electron. Comm. Jpn. Pt. II

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SUMMARYThe national project of ultrahigh-density electronics SI (system integration) technology was started in 1999 and finalized in March 2004. Many research achievements occurred in various areas, such as three-dimensional integration, optoelectronic composite integration, and optimal connection structure design. Among these, the development of the three-dimensional LSI chip stacking technique is especially important in providing a core for future SiP technology. There are also many intensive studies on this topic in research institutions in various countries. The achievements of research in ASET cover a wide range, from the development of process technology to devices approaching practical models, indicating that the technology is highly mature.

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“…Self-oscillations circuit model for equivalent signal delay. (a) Single chip structure; (b) triple chip structure [28]. Fig.…”

Section: Discussionmentioning

confidence: 97%

Section: Evaluation Of Stacked Modulesmentioning

confidence: 98%

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Trends and opportunities of system-in-a-package and three-dimensional integration

Bonkohara

Takahashi

Ishino

2005

Electron. Comm. Jpn. Pt. II

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“…Fine-pitch interconnection, also at a 20 µm pitch for silicon-on-silicon connections with TSVs, has also been reported by [25] and also variety of bonding and electrical interconnection approaches between silicon die in thinned silicon die, die stacks, or packages using silicon reported in [26,27]. In these interconnection examples, anisotropic conductive polymers were used to bond 25 µm thinned dies with 50 µm pitch AuSn bumps.…”

Section: Historical Evolution Of 3d System Integrationmentioning

confidence: 93%

“…In these interconnection examples, anisotropic conductive polymers were used to bond 25 µm thinned dies with 50 µm pitch AuSn bumps. Technical publications have also reported fine-pitch solder connections to copper as a means either to stack thinned silicon chips to other silicon dies or to join dies to silicon packages [25][26][27][28]. An application that leverages TSVs and fine-pitch interconnections with demonstration of functioning memory die stacks has also been presented [29].…”

Section: Historical Evolution Of 3d System Integrationmentioning

confidence: 99%

Three-Dimensional Integration: A More Than Moore Technology

Pangracious

Marrakchi²,

Mehrez

2015

Lecture Notes in Electrical Engineering

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Three-dimensional integrated circuits (3D-ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals and offer a promising solution for reducing both silicon footprint and interconnect length without shrinking the transistors. However, before these advantages can be realized, key technology and CAD challenges of 3D-ICs must be addressed. More specifically, the process required to build circuits with multiple layers of active devices and CAD tools used for design and validation of such circuits. Several such methodologies and CAD tools associated with the design fabrication of 3-D ICs are discussed in this chapter. Few successful 3D-IC design methods and CAD tools and benefits of applying 3D design to the future reconfigurable systems are also discussed in this chapter. IntroductionThe ongoing demand for greater functionality resulting in multiple IC products, longer off-chip interconnects ravage the performance of microelectronic systems. The advent of System-on-Chip (SoC) in the mid 1990s primarily addressed the increasing delay of the off-chip interconnects. Integrating all of the components on a monolithic substrate enhances the overall speed of the system, while decreasing the power consumption. To assimilate disparate technologies, however several difficulties must be surmounted to achieve high yield for the entire system. Additional system requirements for the radio frequency (RF) circuitry, passive elements, and discrete components, such us decoupling capacitors, which are not easily integrated due to performance degradation or size limitations. While Moore's law [1] and the pursuit of ever increasing transistor counts is well known in IC design and manufacturing circles, what is seldom brought to light for others, are the escalating cost and technology challenges associated with this pursuit. Smaller transistors and larger dies have been reasonable answer to this quest in the past. Stacked dies using wire bond connections and flip-chips have even been employed to create system-in-package (SiP) solutions that meet the needs of some. Looking for alternative solutions for next generation designs, that meet the performance, integration, form-factor, manufacturability, and cost requirements, may have begun to look at going up rather than out. With this trend, the Three-dimensional (3D) integration using through-silicon via (TSV) technology has gained much attention. Once the domain of specialist applications, more mainstream users, such as memories, microprocessors ans specialized logic designs are now being considered as TSV candidates. The advantages of 3D-IC integration are better electrical performance, low power consumption, lower area and weight and high performance (Fig. 2.1). Opportunities for Three-Dimensional IntegrationPerformance requirements such as increased band...

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