2020
DOI: 10.1109/led.2020.3004716
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High-Performance Vertical III-V Nanowire MOSFETs on Si With gm > 3 mS/μm

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Cited by 25 publications
(24 citation statements)
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“…The maximum transconductance g m,max of the devices shows state-of-the-art performance, with the best values exceeding 2.5 mS/μm, although they reduce with respect to raised gate position (Figure c). The DC performance of these 12 nm channel diameter devices, with L g = 50 nm, compare well with previously reported vertical GAA MOSFETs, that demonstrated g m,max > 3 mS/μm and R on = 190 Ω·μm for devices scaled to L g = 25 nm (17 nm channel diameter), albeit these devices provided less favorable off-state characteristics with reported SS min = 440 mV/dec . The g m,max vs R on trends (Figure b) confirm the presence of an added ungated resistive regions at the source side for increased spacer thickness L HSQ .…”
Section: Resultssupporting
confidence: 87%
See 1 more Smart Citation
“…The maximum transconductance g m,max of the devices shows state-of-the-art performance, with the best values exceeding 2.5 mS/μm, although they reduce with respect to raised gate position (Figure c). The DC performance of these 12 nm channel diameter devices, with L g = 50 nm, compare well with previously reported vertical GAA MOSFETs, that demonstrated g m,max > 3 mS/μm and R on = 190 Ω·μm for devices scaled to L g = 25 nm (17 nm channel diameter), albeit these devices provided less favorable off-state characteristics with reported SS min = 440 mV/dec . The g m,max vs R on trends (Figure b) confirm the presence of an added ungated resistive regions at the source side for increased spacer thickness L HSQ .…”
Section: Resultssupporting
confidence: 87%
“…The DC performance of these 12 nm channel diameter devices, with L g = 50 nm, compare well with previously reported vertical GAA MOSFETs, that demonstrated g m,max > 3 mS/μm and R on = 190 Ω·μm for devices scaled to L g = 25 nm (17 nm channel diameter), albeit these devices provided less favorable off-state characteristics with reported SS min = 440 mV/dec. 41 The g m,max vs R on trends ( Figure 5 b) confirm the presence of an added ungated resistive regions at the source side for increased spacer thickness L HSQ . 33 The added access resistance, at the source, also serves to reduce the effective voltage drop between the gate and source.…”
Section: Resultsmentioning
confidence: 56%
“…Properties such as high charge carrier mobility and a large range of available band gap values are the reason why III–V semiconductors have become the source for a number of high-performance devices in the microelectronics industries. , InAs, in particular, has an electron mobility which is more than 20 times higher than that of Si, which makes it an optimal material for a new generation of high-speed metal oxide semiconductor (MOS) transistors, especially for radio frequency applications. ,, However, unlike Si, which naturally includes a uniform native oxide and an almost perfect semiconductor-oxide interface, InAs comes along with a high interface trap density that limits the performance of the device. , A promising solution, which has revolutionized the fabrication of III–V MOS gate stacks, was to replace the unwanted native oxide with an ultrathin layer of a material with a high dielectric constant, a so-called high-κ material , such as Al 2 O 3 or HfO 2 , using atomic layer deposition (ALD). In this way, high-performance MOS field effect transistors (MOSFET) based on InGaAs or InAs could be achieved.…”
Section: Introductionmentioning
confidence: 99%
“…[13] shows an OFF-state leakage current of below 1 nA/µm and the ON-state current saturates at a low supply voltage of only 0.5 V. This allows efficient suppression of sneak-path leakage currents while delivering high operation currents [13]. A record high gm > 3 mS/µm and low RON = 190 Ωµm at VDS = 0.5 V have been reported on a scaled III-V VNW-FET with LG = 25 nm and a channel diameter of 17 nm with a similar process used for the selector in this work [14].…”
Section: Introduction Euromorphic Andmentioning
confidence: 75%
“…The favourable III-V material properties combined with the vertical NW geometry allow decoupling the gate and contact lengths from the area footprint leading to higher integration densities. [12][13][14][15][16]. Recently, HfO2 has gained attention as a switching oxide for RRAMs and metal electrodes for RRAMs such as platinum (Pt), titanium nitride (TiN) and indium-tin-oxide (ITO) have been explored [17][18][19][20][21].…”
Section: Introduction Euromorphic Andmentioning
confidence: 99%