High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

Liu, Qianlong; Vinet, M.; Gimbert, J.; Loubet, N.; Wacquez, R.; Grenouillet, L.; Tiec, Y. Le; Khakifirooz, A.; Nagumo, T.; Cheng, K.; Kothari, H.; Chanemougame, D.; Chafik, F.; Guillaumet, S.; Kuss, J.; Allibert, F.; Tsutsui, Gen; Li, J.; Morin, P.; Mehta, S.; Johnson, Rob; Edge, L. F.; Ponoth, S.; Levin, T. M.; Kanakasabapathy, S.; Haran, B.; Bu, H.; Bataillon, J.-L.; Weber, O.; Faynot, O.; Josse, E.; Haond, M.; Kleemeier, W.; Khare, Mukesh; Skotnicki, T.; Luning, S.; Doris, B.; Celik, M.; Sampson, R.

doi:10.1109/iedm.2013.6724592

Cited by 77 publications

(38 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Ultra-thin buried oxide (BOX) silicon-on-insulator (SOI) MOSFETs attract significant interest because of their superior electrical properties: excellent short-channel effect (SCE) immunity and low device-to-device variability [1]. Furthermore, in ultra-thin BOX structures, extremely low-power operations have been demonstrated by utilizing adaptive back biasing [2].…”

Section: Introductionmentioning

confidence: 99%

Direct Evaluation of Self-Heating Effects in Bulk and Ultra-Thin BOX SOI MOSFETs Using Four-Terminal Gate Resistance Technique

Takahashi

Matsuki

Shinada

et al. 2016

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

We demonstrate clear self-heating effects (SHE) of bulk and SOI MOSFETs for various SOI/BOX thicknesses including ultra-thin 6 nm BOX, which was not detected by the AC conductance method, using the four-terminal gate resistance technique. We clarify that the SHE in bulk MOSFETs originates from the degradation of thermal conductivity in a heavily doped well region. The strong chip-temperature dependence of the SHE was observed only in bulk MOSFETs. As results of the chip temperature-dependent SHE of bulk devices and the SHE suppression by BOX thinning, the device temperature of ultrathin BOX SOI MOSFETs is close to that of bulk MOSFETs at an elevated chip temperature, which suggests the thermal advantage of extremely thin BOX structures.

show abstract

Section: Introductionmentioning

confidence: 99%

Direct Evaluation of Self-Heating Effects in Bulk and Ultra-Thin BOX SOI MOSFETs Using Four-Terminal Gate Resistance Technique

Takahashi

Matsuki

Shinada

et al. 2016

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

show abstract

“…On the other hand, pFET devices present a degraded mobility compared to reference devices. It should be said that the series resistances extracted with the Y function methodology [15] were in the range of few decades of Ohm.μm in both sSOI and SOI devices. We argue then that the I eff /I off curves trend can be explained by the impact of strain on carrier mobility rather than by a series resistance effect.…”

Section: Fd-soi Devices Process and Resultsmentioning

confidence: 99%

“…Details of the integration scheme can be found in various publications. 2,[13][14][15] The bottom oxide thickness is 25 nm. The Si on oxide thickness is 7.5 nm.…”

Section: Fd-soi Devices Process and Resultsmentioning

confidence: 99%

Converting SOI to sSOI through Amorphization and Crystallization: Material Analysis and Device Demonstration

Maitrejean¹,

Loubet

Augendre³

et al. 2015

ECS J. Solid State Sci. Technol.

Self Cite

View full text Add to dashboard Cite

Here, we demonstrate a new process to fabricate tensily strained Si On Insulator substrates (sSOI). The process is based on the epitaxial growth of Si 1-x Ge x on SOI substrate, the partial amorphization and crystallization of the Si/Si 1-x Ge x bilayers and the selective removal of the top Si 1-x Ge x film. Si tensile stress higher than 1.4 GPa is obtained. Complementary Metal Oxide Semiconductor Fully Depleted-SOI (CMOS FD-SOI) devices, with gate length lower than 15 nm, were fabricated on top of such substrate. For nFET devices, improvement in mobility is demonstrated with respect to devices built on standard SOI substrates.

show abstract

“…Ge enrichment has been used to generate SiGe on insulator samples and achieve thin compressive strained layer [3]. Ge enrichment starts with a thin oxide layer deposited to stabilize the surface of the SiGe layer, followed by a standard RTO process to oxidize the SiGe and push the Ge atoms in the SOI underneath yielding to 7nm SGOI containing a range of 15-35% Ge [4].…”

Section: B Sige On Utbb Fdsoimentioning

confidence: 99%

Silicon-Germanium (SiGe) composition and thickness determination via simultaneous smallspot XPS and XRF measurements

Lherron

Loubet

Liu

et al. 2014

25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014)

View full text Add to dashboard Cite

The thickness and composition determination of Silicon-Germanium (SiGe) films have been demonstrated using simultaneous X-ray Photoelectron (XPS) and X-ray Fluorescence (XRF) measurements. Measurements of SiGe films in various applications were explored. It is shown that the measurement is sensitive and linear over a much wider range of SiGe thickness, with excellent precision. Long term stability of the measurement is also shown to be very good.

show abstract

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

Cited by 77 publications

References 1 publication

Direct Evaluation of Self-Heating Effects in Bulk and Ultra-Thin BOX SOI MOSFETs Using Four-Terminal Gate Resistance Technique

Direct Evaluation of Self-Heating Effects in Bulk and Ultra-Thin BOX SOI MOSFETs Using Four-Terminal Gate Resistance Technique

Converting SOI to sSOI through Amorphization and Crystallization: Material Analysis and Device Demonstration

Silicon-Germanium (SiGe) composition and thickness determination via simultaneous smallspot XPS and XRF measurements

Contact Info

Product

Resources

About