High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection

Karp, Martin; Podobas, Artur; Jansson, Niclas; Kenter, Tobias; Plessl, Christian; Schlatter, Philipp

doi:10.1109/ipdps49936.2021.00116

Cited by 12 publications

(12 citation statements)

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“…With regards to total runtime, the computation with rematerialization performs around 2x faster than the original version and requires around 33% fewer cycles to make the computation for inputs larger than 2048 elements. Of note is that we are able to saturate the available memory bandwidth for double-precision much earlier than for single-precision, something that was also noted in our previous work and shown in the appendix to [25].…”

Section: With Rematerializationsupporting

confidence: 78%

“…When designing a custom accelerator, such as the SEM solver accelerator we incept in this work, it is crucial to first derive a performance model for said computation. An analytical performance model can help designing accelerator in multiple ways: (i) we can easier understand the bottlenecks of the application, (ii) we can derive the theoretically observable peak performance and also use it to model future (today non-existing) architecture (e.g., [25,50], and (iii)…”

Section: Theoretical Performance Analysismentioning

confidence: 99%

“…Our implementation is made with Intel OpenCL SDK for FPGAs [12], a High-Level Synthesis Tool for Intel FPGAs. We start from our previous work where we implemented the local operation without the gatherscatter operation, in that work we also go into more detail on more practical optimization techniques [25]. For general optimization guidelines for FPGAs, see for example [13,27].…”

Section: Accelerator Implementationmentioning

confidence: 99%

“…As for the implementation of the spectral element method on FPGAs, the core computation has been implemented on both Xilinx and Intel FPGAs [8,25]. However, as these works only optimize the most compute-heavy kernel, and the Xilinx work only evaluates a very high polynomial degree, many of the issues brought up in this work were largely untouched.…”

Section: Related Workmentioning

confidence: 99%

“…While prior works have shown FPGAs to outperform CPUs (and, in some cases, GPUs) on subset of larger applications (smaller kernels, e.g. [25,39,43], we map (for the first time to our knowledge) the entire SEM-based solver to a modern FPGA, including analyzing and modelling its data movement properties from the perspective of reconfigurable systems.…”

Section: Introductionmentioning

confidence: 99%

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A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays

Karp,

Podobas,

Kenter

et al. 2021

Preprint

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The impending termination of Moore's law motivates the search for new forms of computing to continue the performance scaling we have grown accustomed to. Among the many emerging Post-Moore computing candidates, perhaps none is as salient as the Field-Programmable Gate Array (FPGA), which offers the means of specializing and customizing the hardware to the computation at hand.In this work, we design a custom FPGA-based accelerator for a computational fluid dynamics (CFD) code. Unlike prior workwhich often focuses on accelerating small kernels -we target the entire unstructured Poisson solver based on the high-fidelity spectral element method (SEM) used in modern state-of-the-art CFD systems. We model our accelerator using an analytical performance model based on the I/O cost of the algorithm. We empirically evaluate our accelerator on a state-of-the-art Intel Stratix 10 FPGA in terms of performance and power consumption and contrast it against existing solutions on general-purpose processors (CPUs). Finally, we propose a novel data movement-reducing technique where we compute geometric factors on the fly, which yields significant (700+ GFlop/s) single-precision performance and an upwards of 2x reduction in runtime for the local evaluation of the Laplace operator.We end the paper by discussing the challenges and opportunities of using reconfigurable architecture in the future, particularly in the light of emerging (not yet available) technologies.

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Section: With Rematerializationsupporting

confidence: 78%

Section: Theoretical Performance Analysismentioning

confidence: 99%

Section: Accelerator Implementationmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays

Karp,

Podobas,

Kenter

et al. 2021

Preprint

Self Cite

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A Methodology for Evaluating the Energy Efficiency of Post-Moore Architectures

Yepes

Barrios-Hernandez

Steffenel

2022

Communications in Computer and Information Science

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The improvement of computational systems has been based on Moore's law and Dennard's scale, but for more than a decade it has started to fall to a standstill. To maintain the improvement new technologies are proposed, this has established a Post-Moore era. Currently there are different methodologies to evaluate emerging devices and technologies, but the results of these methodologies end up being particular solutions. This paper presents a methodology that can evaluate Post-Moore devices or technologies in an agile way, characterizing an application, choosing a device that meets its needs, selecting tests and parameters that are executed to meet the objectives set by the methodology. The results show how to evaluate the energy efficiency of these new technologies, but the scope of the methodology can cover other needs.

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High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

et al. 2022

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Hardware accelerators based on field programmable gate array (FPGA) and system on chip (SoC) devices have gained attention in recent years. One of the main reasons is that these devices contain reconfigurable logic, which makes them feasible for boosting the performance of applications. High-level synthesis (HLS) tools facilitate the creation of FPGA code from a high level of abstraction using different directives to obtain an optimized hardware design based on performance metrics. However, the complexity of the design space depends on different factors such as the number of directives used in the source code, the available resources in the device, and the clock frequency. Design space exploration (DSE) techniques comprise the evaluation of multiple implementations with different combinations of directives to obtain a design with a good compromise between different metrics. This paper presents a survey of models, methodologies, and frameworks proposed for metric estimation, FPGA-based DSE, and power consumption estimation on FPGA/SoC. The main features, limitations, and trade-offs of these approaches are described. We also present the integration of existing models and frameworks in diverse research areas and identify the different challenges to be addressed. INDEX TERMSComputing models, design space exploration, field programmable gate array (FPGA), system on chip (SoC), power consumption.years (2016-2022) and have been selected based on the topics addressed in this survey. Several papers published before 2016 have been considered because of their contributions to the current literature. C. OUTLINEThe remainder of this paper is organized as follows. Section II briefly presents the most widely used parallel computing models for CPU, GPU, and multicore processors. Section III introduces the FPGA-based reconfigurable hardware accelerator architectures, hardware/software co-design, DSE and metrics, and the techniques to improve latency, area, and power for this technology. In Section IV, we describe previous works on models, methodologies, and frameworks proposed for FPGA/SoC according to their main features: metrics estimation (IV-A), FPGA-based DSE (IV-B), and power consumption estimation (IV-C); and in Section IV-D, we present a summary and discussion. The integration of models and frameworks for FPGA-based reconfigurable hardware accelerators in different research fields is exposed in Section V. Challenges are analyzed in Section VI. Finally, conclusions are presented in Section VII. II. PARALLEL COMPUTING MODELS FOR PERFORMANCE ESTIMATIONComputing models allow to easily analyzing algorithms by simplifying the computational world to a reduced set of parameters that define the cost of arithmetic and memory access operations and communication. These models contribute to the search for efficient algorithms for a given architecture, improving the productivity of designers, programmers, and engineers. A small amount of communication, a small number of operations, and a high degree of parallelism are key points that d...

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High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection

Cited by 12 publications

References 35 publications

A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays

A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays

A Methodology for Evaluating the Energy Efficiency of Post-Moore Architectures

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

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