High-performance software emulation of 1750 A processor

Abstract

We describe a software emulator of the MIL-STD-1750A architecture that executes 1750A code at a rate of about 4 MIPS on a Sun 200jMHz Ultra2 workstation, and effectively several times faster than that when application-specific optimizations are used. A number of optimization techniques were used, including binary translation and an unusual emulation of the 1750A timers and memory management unit. The perfozmance technologies used within the emulator are for the most part applicable to the emulation of other processor architectures.