High‐performance single‐cycle memristive multifunction logic architecture

Yang, Xin; Adeyemo, Adedotun; Jabir, Abusaleh; Mathew, Jimson

doi:10.1049/el.2015.4394

Cited by 13 publications

(9 citation statements)

References 7 publications

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“…7, especially, when the logic inputs are at the switching stages. In [20], [21], we proposed the purely memristive XOR architecture which consists of four memristors M 1 , M 2 , M 3 and M 4 as shown in Fig. 6(a).…”

Section: B Parasitic Effects On Memristive Xor Logic Architecturementioning

confidence: 99%

“…However, by connecting the PMOS transistor (PMOST) to the voltages V L1 and V L2 , the memristive XNOR operation can be realised in Fig. 6(c) [20], [21]. The output of the 1T-4M XOR architecture is demonstrated in Fig.…”

Section: B Parasitic Effects On Memristive Xor Logic Architecturementioning

confidence: 99%

“…The parasitic effects of the generic memristor model on the memristive logic architecture are demonstrated in Section III. With the help of the cascaded XOR structure, Section IV shows that our proposed memristive logic architectures [20], [21] provide more reliable performance as compared to the existing memristive logic technique [18]. The paper is concluded in Section V.…”

Section: Introductionmentioning

confidence: 99%

“…Then, [22]- [24] proposed a generic memristor model with parasitic components and it corresponds more closely to the memristive device in the real world. In this paper, we discuss how the parasitic components of the memristor model effect our proposed memristive logic architectures [20], [21]; and we also present the certain advantages of our proposed 3T-4M logic architecture over the existing 6T-2M logic architecture [18] while dealing with the cascaded XOR structure. For example, delay based Physical Unclonable Function (PUF) [25], [26].…”

Section: Introductionmentioning

confidence: 99%

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Parasitic effects on memristive logic architecture

Yang

Adeyemo

Bala

et al. 2017

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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The most of the memristor based applications which have been proposed so far have not considered the parasitic components. In this paper, we apply a generic memristor model which includes the parasitic effects to our proposed memristive logic architectures. First, we show that the current response of the memristor has the decaying oscillation when the unit step function is applied. Then we demonstrated that our specific memristive logic structure can almost eliminate those effects which are generated by the parasitic components of the memristor. In addition, the propagation delay and the variation of the memristive XOR gate are increased because of the parasitic components. With the delay analysis on cascaded memristive logic design, the experimental results show that our 3T-4M memristive XOR architecture can build the more robust delay based memristive physical unclonable function (PUF) comparing to the existing memristive PUF.keywordsmemristor, hysteresis loop, memristive Logic gate, AND, OR, 3T-4M XOR, parasitic effects, physical unclonable function (PUF).

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Section: B Parasitic Effects On Memristive Xor Logic Architecturementioning

confidence: 99%

Section: B Parasitic Effects On Memristive Xor Logic Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Parasitic effects on memristive logic architecture

Yang

Adeyemo

Bala

et al. 2017

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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“…Memristor can be used in memory [7] as well as logic design [8], [9]due to its retaining proficiency. Moreover, it can also be used in analog circuits [10] and image processing for storage and memory organization due to its nano scale size and low power consumption features [11].…”

Section: Introductionmentioning

confidence: 99%

Learning method for ex-situ training of memristor crossbar based multi-layer neural network

Bala

Adeyemo

Yang

et al. 2017

2017 9th International Congress on Ultra Modern Telecommunications and Control Systems and Workshops (ICUMT)

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Memristor is being considered as a game changer for the realization of neuromorphic hardware systems due to its similarity with biological synapse. Recent studies show that memristor crossbar can provide high density and high performance neural network hardware implementation at low power due to its physical layout, nano scale size and low power consumption feature. This paper describes the training method that can be used for the implementation of memristive multi-layer neural network with ex-situ method. We mimic the behavior of memristor crossbar in software training process to achieve more accurate and close computations to hardware. Voltage divider has been used to calculate the dot product in this method. To demonstrate the accuracy and effectiveness of this method, different patterns and non-separable functions using memristor crossbar structures are simulated. The results demonstrate that more accurate computations can be produced using this learning method for ex-situ. It also reduces the learning time of functions.

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Low power memristive gas sensor architectures with improved sensing accuracy

et al. 2022

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Memristive devices, traditionally considered for memory, logic, and neuromorphic systems, are exhibiting many interesting properties for applications in a variety of areas, such as in sensing chemicals. However, any realistic approach based on these devices must take into account their susceptibility to process and parametric variations. When used for sensing purposes this, together with wire resistance, can significantly degrade their sensing accuracy. To this end, we propose novel memristive gas sensor architectures that can significantly reduce these effects in a predictable manner, while improving accuracy and overall power consumption. Additionally, we show that in the absence of gasses this architecture can also be configured to realize multifunction logic operations as well as Complementary Resistive Switch with low hardware overhead, thereby enhancing resource reusability. We also present a method for further improving power consumption and measurability by manipulating a device’s internal barrier. Our results show that the proposed architecture is significantly immune to process and parametric variations compared to a single sensor and almost unaffected by wire resistance, while offering much higher accuracy and much lower power consumption compared to existing techniques.

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High‐performance single‐cycle memristive multifunction logic architecture

Cited by 13 publications

References 7 publications

Parasitic effects on memristive logic architecture

Parasitic effects on memristive logic architecture

Learning method for ex-situ training of memristor crossbar based multi-layer neural network

Low power memristive gas sensor architectures with improved sensing accuracy

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