High-performance SIMT code generation in an active visual effects library

Cornwall, Jay L. T.; Howes, Lee; Parsonage, Phil; Nicoletti, Bruno

doi:10.1145/1531743.1531772

Cited by 9 publications

(2 citation statements)

References 17 publications

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“…Most prior image processing languages and systems have focused on efficient expression of individual kernels, as well as simple fusion in the absence of stencils [6,8,23,27]. Recently, Cornwall et al demonstrated fast GPU code generation for image processing code using polyhedral optimization [7].…”

Section: Prior Workmentioning

confidence: 99%

Halide

et al. 2013

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Image processing pipelines combine the challenges of stencil computations and stream programs. They are composed of large graphs of different stencil stages, as well as complex reductions, and stages with global or data-dependent access patterns. Because of their complex structure, the performance difference between a naive implementation of a pipeline and an optimized one is often an order of magnitude. Efficient implementations require optimization of both parallelism and locality, but due to the nature of stencils, there is a fundamental tension between parallelism, locality, and introducing redundant recomputation of shared values.We present a systematic model of the tradeoff space fundamental to stencil pipelines, a schedule representation which describes concrete points in this space for each stage in an image processing pipeline, and an optimizing compiler for the Halide image processing language that synthesizes high performance implementations from a Halide algorithm and a schedule. Combining this compiler with stochastic search over the space of schedules enables terse, composable programs to achieve state-of-the-art performance on a wide range of real image processing pipelines, and across different hardware architectures, including multicores with SIMD, and heterogeneous CPU+GPU execution. From simple Halide programs written in a few hours, we demonstrate performance up to 5× faster than hand-tuned C, intrinsics, and CUDA implementations optimized by experts over weeks or months, for image processing applications beyond the reach of past automatic compilers.

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Section: Prior Workmentioning

confidence: 99%

Halide

et al. 2013

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“…For example, both Lee et al [12] and Svensson et al [19] present a functional language. Others, such as Cornwall et al introduce a new framework [6]. These solutions all introduce a learning curve, reducing the chance for adoption by programmers.…”

Section: Related Workmentioning

confidence: 99%

Skeleton-based automatic parallelization of image processing algorithms for GPUs

Nugteren

Corporaal

Mesman

2011

2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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Abstract-Graphics Processing Units (GPUs) are becoming increasingly important in high performance computing. To maintain high quality solutions, programmers have to efficiently parallelize and map their algorithms. This task is far from trivial, leading to the necessity to automate this process.In this paper, we present a technique to automatically parallelize and map sequential code on a GPU, without the need for code-annotations. This technique is based on skeletonization and is targeted at image processing algorithms. Skeletonization separates the structure of a parallel computation from the algorithm's functionality, enabling efficient implementations without requiring architecture knowledge from the programmer. We define a number of skeleton classes, each enabling GPU specific parallelization techniques and optimizations, including automatic thread creation, on-chip memory usage and memory coalescing.Recently, similar skeletonization techniques have been applied to GPUs. Our work uses domain specific skeletons and a finergrained classification of algorithms. Comparing skeleton-based parallelization to existing GPU code generators in general, we potentially achieve a higher hardware efficiency by enabling algorithm restructuring through skeletons.In a set of benchmarks, we show that the presented skeletonbased approach generates highly optimized code, achieving high data throughput. Additionally, we show that the automatically generated code performs close or equal to manually mapped and optimized code. We conclude that skeleton-based parallelization for GPUs is promising, but we do believe that future research must focus on the identification of a finer-grained and complete classification.

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