High Performance Seesaw Torsional CMOS-MEMS Relay Using Tungsten VIA Layer

Riverola, M.; Torres, F.; Uranga, A.; Barniol, N.

doi:10.3390/mi9110579

Cited by 2 publications

(2 citation statements)

References 20 publications

(43 reference statements)

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“…First, each film was deposited using wafer defining contact holes to confirm the bottom coverage of IMP Ti and CVD TiN. The contact holes were defined in accordance with the 150 nm-class logic contact design rules [20,21]. Figure 1 shows the bottom coverage of IMP Ti and CVD TiN.…”

Section: Resultsmentioning

confidence: 99%

Effect of Contact Plug Deposition Conditions on Junction Leakage and Contact Resistance in Multilevel CMOS Logic Interconnection Device

et al. 2020

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Here, we developed the optimal conditions in terms of physical and electrical characteristics of the barrier and tungsten (W) deposition process of a contact module, which is the segment connecting the device and the multi-layer metallization (MLM) metal line in the development of 100 nm-class logic devices. To confirm its applicability to the logic contact of barrier and W films, a contact hole was formed, first to check the bottom coverage and the filling status of each film, then to check the electrical resistance and leakage characteristics to analyze the optimal conditions. At an aspect ratio of 3.89:1, ionized metal plasma (IMP) Ti had a bottom coverage of 40.9% and chemical vapor deposition (CVD) titanium nitride (TiN) of 76.2%, confirming that it was possible to apply the process to 100 nm logic contacts. W filling was confirmed, and a salicide etching rate (using Radio Frequency (RF) etch) of 13–18 Å/s at a 3.53:1 aspect ratio was applied. The etching rate on the thermal oxide plate was 9 Å/s. As the RF etch amount increased from 50–100 Å, the P active resistance increased by 0.5–1 Ω. The resistance also increased as the amount of IMP Ti deposition increased to 300 Å. A measurement of the borderless contact junction leakage current indicated that the current in the P + N well increased by more than an order of magnitude when IMP Ti 250 Å or more was deposited. The contact resistance value was 0.5 Ω. An AC bias improved the IMP Ti deposition rate by 10% in bottom coverage, but there was no significant difference in contact resistance. In the case of applying IMP TiN, the overall contact resistance decreased to 2 Ω compared to CVD TiN, but the distribution characteristics were poor. The best results were obtained under the conditions of RF etch 50 Å, IMP Ti 200 Å, and CVD TiN 2 × 50 Å.

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Section: Resultsmentioning

confidence: 99%

Effect of Contact Plug Deposition Conditions on Junction Leakage and Contact Resistance in Multilevel CMOS Logic Interconnection Device

et al. 2020

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“…In the work of Perelló-Roig et al [7], the design, fabrication, and electrical characterization of an electrostatically actuated and capacitive sensed 2-MHz plate resonator structure that exhibits a predicted mass sensitivity of ~250 pg·cm −2 ·Hz −1 is presented. The work of Riverola et al [8] presents a tungsten seesaw torsional relay monolithically integrated in a standard 0.35 μm CMOS technology capable of a double hysteretic switching cycle, providing compactness for mechanical logic processing. Chan Jo and Young Choi [9] present a novel encapsulation method of NEM memory switches based on alumina passivation layers being fully compatible with the CMOS baseline process that allows locating NEM memory switches in any place, making circuit design more volume-efficient.…”

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confidence: 99%