High-performance Reconfigurable DNN Accelerator on a Bandwidth-limited Embedded System

Abstract

Deep convolutional neural networks (DNNs) have been widely used in many applications, particularly in machine vision. It is challenging to accelerate DNNs on embedded systems because real-world machine vision applications should reserve a lot of external memory bandwidth for other tasks, such as video capture and display while leaving little bandwidth for accelerating DNNs. In order to solve this issue, in this study, we propose a high-throughput accelerator, called reconfigurable tiny neural-network accelerator (ReTiNNA) for the bandwidth-limited system, and present a real-time object detection system for the high-resolution video image. We first present a dedicated computation engine that takes different data mapping methods for various filter types to improve data reuse and reduce hardware resources. We then propose an adaptive layer-wise tiling strategy that tiles the feature maps into strips to reduce the control complexity of data transmission dramatically and to improve the efficiency of data transmission. Finally, a design space exploration (DSE) approach is presented to explore design space more accurately in the case of insufficient bandwidth to improve the performance of the low-bandwidth accelerator. With a low bandwidth of 2.23 GB/s and a low hardware consumption of 90.261K LUTs and 448 DSPs, ReTiNNA can still achieve a high performance of 155.86 GOPS on VGG16 and 68.20 GOPS on ResNet50, which is better than other state-of-the-art designs implemented on FPGA devices. Furthermore, the real-time object detection system can achieve a high object detection speed of 19 fps for high-resolution video.

Brain-inspired methods for achieving robust computation in heterogeneous mixed-signal neuromorphic processing systems

“…With the advent of deep networks for artificial intelligence [1], and the increasing need of special purpose low-power devices that can complement general-purpose power-hungry computers in 'edge computing' applications [2, 3], several types of event-based approaches for implementing spiking neural networks (SNNs) in dedicated hardware have been proposed [4][5][6][7][8][9]. While many of these approaches are focusing on supporting the simulation of large scale SNNs [4,6,9], on converting rate-based artificial neural networks (ANNs) into their spike-based equivalent networks [10][11][12], or on processing digitally stored data with digital hardware implementations [13][14][15][16][17], the original neuromorphic engineering approach, first introduced in the early '90 s, proposed to implement biologically plausible SNNs by exploiting the physics of subthreshold analog complementary metal-oxide-semiconductor (CMOS) circuits to directly emulate the bio-physics of biological neurons and synapses [18,19].…”