“…Thus, low-cost FPGA designs have focused on reducing this parameter with a sequential architecture, where a high speed internal clock is required to improve the resolution of τ , limiting its width to a few nanoseconds [11], [12]. On the other hand, low-cost architectures based on logic gates (combinational coincidence evaluation) have been proposed as coincidence counters by reducing τ to few tens of nanoseconds [13], then improving to sub nanosecond resolution using external circuits [14]. FPGAs using sequential architectures are capable to acquire and transmit electronic signals in the nanosecond regime [15]- [17], integrating arithmetic processes, and providing flow control over different clocks within a single integrated circuit (IC) [18], [19], even being used to manage different quantum information systems, such as quantum routing [20], [21], quantum random generation [22], [23], and quantum key distribution [24]- [26].…”