“…At the transistor level, they translate into specifications for the OFF current, i.e., 599 must be 100 nA/µm in the case of HP devices and 100 pA/µm in the case of LP devices [40] [41]. [73] [74], holes in SOI [74], holes in germanium-on-insulator [75], graphene on SiO2 [76], graphene embedded in h-BN [61], InAs [77], WSe2 [78] [79], WS2 [81], black phosphorus [82] [83], MoS2 [84] [85], c) Experimental Rc of different 2D materials and thin body semiconductors compared with expectations of the ITRS. Data sources: ITRS [40], MoS2 [84], MoS2-2H/Au and MoS2-1T/Au [86], MoS2/Au [87] [88] and MoS2/Ni [87], Pd-Graphene [90], d) Scatter plot of delay time and power-delay product for High Performance Logic of different 2D Heterostructurebased FET and comparison with ITRS 2015 e) Scatter plot of delay time and power-delay product for Low Standby Power logic of different 2D Heterostructure-based FET and comparison with ITRS 2015.…”