High-performance microelectronic substrate verification using probe testers

Abstract

We propose an improved algorithm for highperformance substrate verification utilizing multi-probe testers. Previous works[3, 91 only consider some minimum test sets with complete fault coverage to optimize probe routes. Since there exist numerous such sets for a design, our algorithm dynamically selects preferred ones using a linear validation routine during the probe route optimization phase. By considering the test generation and the probe scheduling simultaneously, the algorithm has demonstrated its superiority over previous works.

Formulation and heuristic algorithms for multi-chip module substrate testing

“…Because of the high-density assembly, MCM has several advantages in terms of power consumption, package volume, and so on [4]. However, high-density assembly causes faults on MCM substrates [5][6][7][8]. These faults are classified as open faults, short faults, near-open faults, and near-short faults (Fig.…”