High-performance, low-power architecture for scalable radix 2 montgomery modular multiplication algorithm

Ibrahim, Atef; Gebali, Fayez; Elsimary, Hamed; Nassar, Amin

doi:10.1109/cjece.2009.5599422

Cited by 18 publications

(12 citation statements)

References 19 publications

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“…2) allocating a time value to each node in the DG using a specific timing or scheduling function. 3) mapping several nodes of the DG to a processing element (PE) to form the systolic/semi-systolic array [20,25,26,27,28,29,30]. The DG of the unified multiplication and squaring algorithm over GFð2 m Þ can be extracted from the recursive Eqs.…”

Section: Proposed Semi-systolic Array Architecture Of the Unified Algmentioning

confidence: 99%

“…The DG of the unified multiplication and squaring algorithm over GFð2 m Þ can be extracted from the recursive Eqs. 15, (24), (25), (26), (27), (30), and (31). The extracted DG based on these equations is shown in Fig.…”

Section: Proposed Semi-systolic Array Architecture Of the Unified Algmentioning

confidence: 99%

“…The upper part consists of the upper l rows of the DG (rows with the light red nodes) and it computes the coefficients of C, H, G, V, U according to Eqs. (15), (24), (25), (26), (27), respectively. The lower part consists of the last row of the DG (row with the brown nodes) and it computes the coefficients of P and S according to Eqs.…”

Section: Proposed Semi-systolic Array Architecture Of the Unified Algmentioning

confidence: 99%

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Efficient parallel semi-systolic array structure for multiplication and squaring in GF(2m)

Ibrahim

Tariq

Ahmad

et al. 2019

IEICE Electron. Express

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In this paper, we develop an efficient parallel semi-systolic array structure to concurrently compute multiplication and squaring operations in the binary extension field, GF(2 m), for efficient modular exponentiations. The proposed array is well suited to VLSI implementation that it has a regular structure as well as local communications between its processing elements. The obtained results show that the proposed array structure achieves a significant reduction in area-time (AT) complexity by at least 95.9% over the corresponding existing structures.

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Section: Proposed Semi-systolic Array Architecture Of the Unified Algmentioning

confidence: 99%

Section: Proposed Semi-systolic Array Architecture Of the Unified Algmentioning

confidence: 99%

Section: Proposed Semi-systolic Array Architecture Of the Unified Algmentioning

confidence: 99%

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Efficient parallel semi-systolic array structure for multiplication and squaring in GF(2m)

Ibrahim

Tariq

Ahmad

et al. 2019

IEICE Electron. Express

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“…This approach starts by obtaining the dependency graph (DG) for the intended algorithm and assigning a time value to each node in the DG using a scheduling function as explained by authors in [14,15,16,17,18,20]. The approach ends by projecting several nodes of the DG to a processing element (PE) to constitute the systolic array [14,17,19,20,21,22].…”

Section: Proposed Systolic Array Design Of the Division Algorithmmentioning

confidence: 99%

“…The systolic array architecture can be extracted by choosing the scheduling vector S ¼ ½1 0 and the projection vector P ¼ ½0 1 T for the DG. These vectors are obtained from applying the approach previously reported by authors in [14,17,20,21,22]. Fig.…”

Section: Proposed Systolic Array Design Of the Division Algorithmmentioning

confidence: 99%

New systolic array architecture for finite field division

Ibrahim

Elsimary

Gebali

2018

IEICE Electron. Express

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This paper proposes a new systolic array architecture to perform division operations over GF(2 m ) based on the modified Stein's algorithm. The systolic structure is extracted by applying a regular approach to the division algorithm. This approach starts by obtaining the dependency graph for the intended algorithm and assigning a time value to each node in the dependency graph using a scheduling function and ends by projecting several nodes of the dependency graph to a processing element to constitute the systolic array. The obtained design structure has the advantage of reducing the number of flip-flops required to store the intermediate variables of the algorithm and hence reduces the total gate counts to a large extent compared to the other related designs. The analytical results show that the proposed design outperforms the related designs in terms of area (at least 32% reduction in area) and speed (at least 60% reduction in the total computation time) and has the lowest AT complexity that ranges from 80% to 94%.

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A Modified Bit-Serial Montgomery Multiplier Algorithm in Fault Detection Method

Prabu

Shanmugalakshmi²

2011

Lecture Notes in Electrical Engineering

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High-performance, low-power architecture for scalable radix 2 montgomery modular multiplication algorithm

Cited by 18 publications

References 19 publications

Efficient parallel semi-systolic array structure for multiplication and squaring in GF(2<i><sup>m</sup></i>)

Efficient parallel semi-systolic array structure for multiplication and squaring in GF(2<i><sup>m</sup></i>)

New systolic array architecture for finite field division

A Modified Bit-Serial Montgomery Multiplier Algorithm in Fault Detection Method

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