High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

Abstract

High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uni-axial strain and low resistance NiSi technique, enhanced by a slit under the slim and high young's modulus(YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (R sd ) reduction. The junction profile was also carefully optimized for low leakage current. As a result of a 12% mobility improvement and a 30% R sd reduction, enhancements of 19 and 14% and I on (@I off = 5 nA/µm) of 620 and 830 µA/µm were achieved for NMOS at 0.85 and 1.0V, respectively. As a result of a 45% mobility improvement and a 25% R sd reduction, the enhancements of 32 and 22% and I on of 330 and 440 µA/µm were achieved for PMOS at 0.85 and 1.0V, respectively. These results are the best I on -I off tradeoff characteristics among the recent LOP transistors. IntroductionHuge markets for battery-operated applications, multi-core LSIs and SoCs with low cost packaging, require both performance enhancement and reduction of the operation power of integrated transistors. In order to find a solution to these requirements, we developed high-performance LOP transistors characterized by low V dd operation to reduce the dynamic (CV dd

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Investigation of analogue performance for process-induced-strained PMOSFETs

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