High performance, low-cost chip-on-board (COB) FDDI transmitter and receiver for avionics applications

Chan, Eric Y.; Le, Quan; Beranek, M.W.

doi:10.1109/ectc.1998.678726

Cited by 6 publications

(5 citation statements)

References 16 publications

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“…Typical values are 10 −6 to 10 −13 errors/bit, although error rates in the field are said to vary dramatically. Some standards for optical networks specify maximum allowable BERs, such as 2.5 * 10 −10 in the Boeing ARINC 636 standard [11] and 10 −12 for Gigabit Ethernet [40]. Copper BERs are typically higher.…”

Section: Network Mediummentioning

confidence: 99%

Coverage and the Use of Cyclic Redundancy Codes in Ultra-Dependable Systems

Paulitsch

Morris

Hall

et al.

2005 International Conference on Dependable Systems and Networks (DSN'05)

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A Cyclic Redundancy Code (CRC), when used properly, can be an effective and relatively inexpensive method to detect data corruption across communication channels. However, some systems use CRCs in ways that violate common assumptions made in analyzing CRC effectiveness, resulting in an overly optimistic prediction of system dependability. CRCs detect errors with some finite probability, which depends on factors including the strength of the particular code used, the bit-error rate, and the message length being checked. Common assumptions also include a passive network inter-stage, explicit data words, memoryless channels, and random independent symbol errors. In this paper we identify some examples of CRC usage that compromise ultra-dependable system design goals, and recommend alternate ways to improve system dependability via architectural approaches rather than error detection coding approaches.

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Section: Network Mediummentioning

confidence: 99%

Coverage and the Use of Cyclic Redundancy Codes in Ultra-Dependable Systems

Paulitsch

Morris

Hall

et al.

2005 International Conference on Dependable Systems and Networks (DSN'05)

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“…The bit error rate class includes faults from jitter and amplitude disturbances on the network. Three optical standards give worst-case BERs ranging from 10 −12 to 10 −10 [9], [23], [35]; we study a less pessimistic range of 10 −13 to 10 −11 . The fourth class, electromagnetic interference, includes correlated burst errors [30], [17], [18].…”

Section: Protocol Overview and Related Workmentioning

confidence: 99%

“…This is comparable to the size of protocol controllers. For example, the TTP-C2NF revision 1.2 chip [26], [11] 10 −10 , 10 −9 , 10 −8 /bit-hr BER [9], [23], [35] 10 −13 , 10 −12 , 10 −11 err/bit Lightning [12] 4*10 −4 /hr has 40 kBytes of SRAM and 32 kBytes of ROM [2]. We perform sensitivity analysis for 256 kBytes.…”

Section: Fault Models and Mappingsmentioning

confidence: 99%

Design Time Reliability Analysis of Distributed Fault Tolerance Algorithms

Latronico

Koopman

2005 International Conference on Dependable Systems and Networks (DSN'05)

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Designing a distributed fault tolerance algorithm requires careful analysis of both fault models and diagnosis strategies. A system will fail if there are too many active faults, especially active Byzantine faults. But, a system will also fail if overly aggressive convictions leave inadequate redundancy. For high reliability, an algorithm's hybrid fault model and diagnosis strategy must be tuned to the types and rates of faults expected in the real world. We examine this balancing problem for two common types of distributed algorithms: clock synchronization and group membership. We show the importance of choosing a hybrid fault model appropriate for the physical faults expected by considering two clock synchronization algorithms. Three group membership service diagnosis strategies are used to demonstrate the benefit of discriminating between permanent and transient faults. In most cases, the probability of failure is dominated by one fault type. By identifying the dominant cause of failure, one can tailor an algorithm appropriately at design time, yielding significant reliability gain.

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“…At Boeing, a new avionics transmitter and receiver packaging 2.A.6-2 concept based on chip-on-board (COB) technology resulted in a lower-cost design [21]. The chip-onboard package utilized large format multi-chip module laminate (MCM-L) substrates and glob top encapsulation of the integrated circuits.…”

Section: Second Generation Legacy Avionics Packaging Lesson's Learnedmentioning

confidence: 99%

Future generation military avionics fiber optics photonics packaging challenges

Beranek

2007

2007 IEEE/AIAA 26th Digital Avionics Systems Conference

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The military/aerospace platform operational environment challenges the creativity of fiber optic module packaging engineers as they endeavor to develop and mature new active and passive singlemode fiber optic and photonic components for next generation avionics networking applications. Low sales and manufacturing volumes inherent to avionics combined with lack of standard interface specifications for current and next generation fiber optic local area network architectures and subsystems makes it difficult for avionics suppliers to justify upfront research and development (R&D) investment in advanced fiber optics and photonics packaging technology.

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High performance, low-cost chip-on-board (COB) FDDI transmitter and receiver for avionics applications

Cited by 6 publications

References 16 publications

Coverage and the Use of Cyclic Redundancy Codes in Ultra-Dependable Systems

Coverage and the Use of Cyclic Redundancy Codes in Ultra-Dependable Systems

Design Time Reliability Analysis of Distributed Fault Tolerance Algorithms

Future generation military avionics fiber optics photonics packaging challenges

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