High-performance logarithmic converters using novel two-region bit-level manipulation schemes

Juang, Tso-Bing; Meher, Pramod Kumar; Jan, Kai-Shiang

doi:10.1109/vdat.2011.5783555

Cited by 26 publications

(27 citation statements)

References 14 publications

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“…Use of more accurate approximation methods of course leads to better error detection capabilities. A more exact but still very hardwareefficient approximation method has been proposed in [19]. The error-detection capabilities using this approach are better of course than the approaches described above.…”

Section: Logarithmic Checking Using Other Approximation Methodsmentioning

confidence: 99%

“…When checking parallel multipliers with this method the log 2 function values also have to be computed in one clock cycle. For this purpose different log 2 -converters have been proposed which approximate the exact log 2 by hardware, for example in [18] or [19]. Due to approximation errors, even in the case that the result of the multiplication (Z) is correct, the error signal in Fig.…”

Section: Logarithmic Checkingmentioning

confidence: 99%

“…For every pair of input values (X, Y ) errors will not be detected until they cause the error-signal e to go beyond these limits. In turn, if the correct result Z is disturbed by an error E the detection of this erroneous result Z e (see equation (19)) is dependent on the value of E but also on the value of of the error-signal e (X, Y ).…”

Section: A Logarithmic Checking Using Mitchell Approximationmentioning

confidence: 99%

See 2 more Smart Citations

Concurrent Error Detection in Multipliers by Using Reduced Wordlength Multiplication and Logarithms

Uhl

Becker

2013

2013 Euromicro Conference on Digital System Design

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Checking multiplication by using logarithms has already been proposed in literature but until now it has not been used widely in practice nor have different implementations been evaluated or compared. In this paper we will analyse the error detection capability of different implementations of logarithmic checking. Based on the results we propose a new way of checking multiplication. It uses normalised and wordlength reduced operands which are multiplied by a smaller multiplier in order to estimate the result of the multiplier to be checked. The estimated result is compared to the result of the multiplier by the difference of their base 2 logarithms. This approach enables the use of inaccurate approximations for the base 2 logarithm computation and improves error detection compared to standard logarithmic checking. The error detection capability can be adjusted to the application's need for error detection by choosing the wordlength of the normalised operands. The error detection capability and the hardware overhead of this method are compared with the ones of known logarithmic checking methods.

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Section: Logarithmic Checking Using Other Approximation Methodsmentioning

confidence: 99%

Section: Logarithmic Checkingmentioning

confidence: 99%

Section: A Logarithmic Checking Using Mitchell Approximationmentioning

confidence: 99%

See 1 more Smart Citation

Concurrent Error Detection in Multipliers by Using Reduced Wordlength Multiplication and Logarithms

Uhl

Becker

2013

2013 Euromicro Conference on Digital System Design

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“…The pictorial representation of logarithm multiplication is shown in Figure 1. Many methods regarding binary to logarithmic conversion and vice versa have been discussed in the last few years [18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35]. Error creates at the time of logarithmic and antilogarithmic conversion [10].…”

Section: Introductionmentioning

confidence: 99%

An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

Nandan¹

2020

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Digital Signal Processing (DSP) applications demand error-free and compact hardware architecture of arithmetic operations. A logarithmic operation provides an efficient option in place of binary arithmetic. In this paper, it is suggested that 11-region and 17-region error correction schemes for developing an efficient antilogarithm converter. It is used for developing the most accurate and compact logarithm multiplier which is used in the DSP processor. Implementations of reported and proposed designs are investigate based on accuracy and hardware overhead and it found outperform in comparisons of previously reported designs. The proposed 11-region converter involves 61% less Area Delay Product (ADP) and 49.82% less energy in comparisons of the reported 11-region antilogarithmic converter and 17-region converter involves 48.02% less ADP and 32.53% less energy in comparisons of the reported 14-region antilogarithmic converter. The proposed antilogarithmic converter achieves 1.697% and 1.084% error for 11-region and 17-region designs respectively than of reported designs of 1.876% and 1.351% for 11-region and 17region respectively.

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“…Work has been done to reduce the conversion error. One strategy is to use a multi-step function to further increase the conversion accuracy [5][6][7][8]. SanGregory et al [9] used another curve to approximate the logarithmic curve instead of the linear function used for the generation of the fraction part.…”

Section: Introductionmentioning

confidence: 99%

Calibration method to reduce the error in logarithmic conversion with its circuit implementation

Zhao

Srivastava

Peng

et al. 2018

IET Circuits, Devices & Systems

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Here, based on Mitchell's logarithmic conversion, the authors propose a fast calibration method using a fixed binary code with case judgement, which suppresses the conversion error. The authors developed a highly paralleled circuit serving the proposed calibration method. Differential cascade voltage switch logic (DCVSL) is used to work in both high-speed logic and adiabatic logic and trade-off between power dissipation and operation speed. In addition, a low-cost adiabatic clock generator without any passive component is presented to support a four-phase sine clock for the adiabatic logic operation. An 8-bit logarithmic converter is designed in TSMC 180 nm CMOS. Post-simulation results show that the proposed calibration can reduce the conversion error to 1.55% based on Mitchell's algorithm, the power dissipation varies between 1.12 and 3.709 mW, and the delay is 1.82 ns under operational DCVLS.

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High-performance logarithmic converters using novel two-region bit-level manipulation schemes

Cited by 26 publications

References 14 publications

Concurrent Error Detection in Multipliers by Using Reduced Wordlength Multiplication and Logarithms

Concurrent Error Detection in Multipliers by Using Reduced Wordlength Multiplication and Logarithms

An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

Calibration method to reduce the error in logarithmic conversion with its circuit implementation

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