High performance interpolation filter using direct computation

El-Azeem, Ratshih S. Abd; El-Moursy, Magdy A.; Nassar, Amin; Gharib, A.; El-Kheir, Nahla T. Abou; El-Kharashi, Moataz S.

doi:10.1109/idt.2016.7843026

Cited by 3 publications

(1 citation statement)

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“…The number of LUTs exponentially depends on the data word size. Abd El‐Azeem , et al presented a computational filter (CF) that employs a sample calculation functional block [14]. This CF significantly reduces the hardware requirements to realise an interpolation filter.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Systolic array design space exploration of interpolators for multi‐rate systems

Shoukry

Gebali

Agathoklis

2019

IET Circuits, Devices & Systems

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This study presents the development and comparison of interpolator systolic array designs and implementations. Systematic methodology was applied to the difference equations defining the interpolator algorithm. A dependence graph for the interpolator was obtained that combined the upsampler and the anti-imaging filter. Different data scheduling and projection operations were developed. Nine systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation. Field-programmable gate array implementations for the conventional and proposed designs confirm that the proposed interpolator implementation requires no more than 61.7% of the hardware resources required in the conventional design and are at least 63.9% faster than the conventional design.

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Section: Introduction and Related Workmentioning

confidence: 99%